EL5420CS-T13 데이터 시트보기 (PDF) - Elantec -> Intersil
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EL5420CS-T13 Datasheet PDF : 13 Pages
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EL5220C, EL5420C
12MHz Rail-to-Rail Input-Output Op Amps
JEDEC JESD51-3 and SEMI G42-88 (Single Layer) Test
Board
1200
MAX TJ=125°C
1000
833mW
SO14
θJA=120°C/W
800
667mW
600 606mW
400 485mW
LPP16
θJA=150°C/W
TSSOP14
θJA=165°C/W
200
MSOP8
θJA=206°C/W
0
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Figure 4. Package Power Dissipation vs
Ambient Temperature
JEDEC JESD51-7 High Effective Thermal Conductivity (4-
Layer) Test Board
(LPP exposed diepad soldered to PCB per JESD51-5)
3
2.500W
2.5
2
1.5
40°CL/WPP16
1
0.5
0
0
25
50
75 85 100
125
150
Ambient Temperature (°C)
Figure 5. Package Power Dissipation vs
Ambient Temperature
Unused Amplifiers
It is recommended that any unused amplifiers in a dual
and a quad package be configured as a unity gain fol-
lower. The inverting input should be directly connected
to the output and the non-inverting input tied to the
ground plane.
Driving Capacitive Loads
The EL5220C and EL5420C can drive a wide range of
capacitive loads. As load capacitance increases, how-
ever, the -3dB bandwidth of the device will decrease and
the peaking increase. The amplifiers drive 10pF loads in
parallel with 10kΩ with just 1.5dB of peaking, and
100pF with 6.4dB of peaking. If less peaking is desired
in these applications, a small series resistor (usually
between 5Ω and 50Ω) can be placed in series with the
output. However, this will obviously reduce the gain
slightly. Another method of reducing peaking is to add a
“snubber” circuit at the output. A snubber is a shunt load
consisting of a resistor in series with a capacitor. Values
of 150Ω and 10nF are typical. The advantage of a snub-
ber is that it does not draw any DC load current or
reduce the gain
Power Supply Bypassing and Printed Circuit
Board Layout
The EL5220C and EL5420C can provide gain at high
frequency. As with any high-frequency device, good
printed circuit board layout is necessary for optimum
performance. Ground plane construction is highly rec-
ommended, lead lengths should be as short as possible
and the power supply pins must be well bypassed to
reduce the risk of oscillation. For normal single supply
operation, where the VS- pin is connected to ground, a
0.1µF ceramic capacitor should be placed from VS+ to
pin to VS- pin. A 4.7µF tantalum capacitor should then
be connected in parallel, placed in the region of the
amplifier. One 4.7µF capacitor may be used for multiple
devices. This same capacitor combination should be
placed at each supply pin to ground if split supplies are
to be used.
12
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