MSM7661BGS-BK 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM7661BGS-BK

NTSC/PAL Digital Video Decoder

Oki Electric Industry 

¡ Semiconductor

MSM7661B

PIN DESCRIPTIONS

Pin

1 to 8

9 to 16

17

18

19

20

21 to 24

25

26

27

28

29

30

31

32

Symbol Type

Description

CD[0 to 7] I Chrominance signal input pin (valid only for S video input)

Set each pin to "L" level at composite signal input.

CVBS[0 to 7] I Composite signal input pin

Luminance signal is input for S video input.

VDD

GND

SCL

I I2C-bus clock pin

SDA

I/O I2C-bus data pin

MODE[0 to 3] I Mode input pins. These pins are internally pulled-down.

MODE[3] 0: composite

MODE[2] 0: NTSC

1: S video

1: PAL

MODE[1:0] 00: ITU-R601

01: Square Pixel

10: 4Fsc (only for NTSC)

11: none

If ITU-R signals are input when registers are set to automatic NTSC/PAL

recognition mode, NTSC/PAL is automatically recognized irrespective of

MODE2 setting.

RESET_L

I System reset pin (active at "L")

PLLSEL

I Unused.

Fixed to "H" externally.

CLKSEL

I Clock select input pin.

"L" Æ double-speed 27 MHz, "H" Æ ordinary 13.5 MHz

TEST1

I Input pin for testing. Normally "L". Internally pulled down.

SLEEP

I Sleep mode setting pin. Normally "L". Internally pulled down.

TE

I Input pin for testing. Normally "L". Internally pulled down.

GND

VDD

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