SPT2110SCT 데이터 시트보기 (PDF) - Signal Processing Technologies

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SPT2110SCT

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Signal Processing Technologies 

Table V - MPU Interface Description

Signal Name Abbreviation

CHIP SELECT CS_

REGISTER

SELECT

WRITE

READ

DATA(7-0)

RS

WR_

RD_

D7-0

Description

The Chip Select signal (active low logic) enables further action by the chip from the other

control lines This means the chip needs to process (recognize) one of the following

control signals: RS, WR_ or RD_.

The Register Select signal (active high logic) enables access to the Command Register

that the address register is holding. When this signal is low it enables the address data

register.

The Write signal (active low logic) transfers the data on the data bus into the address or

command data register (depending on the level of RS).

The Read signal (active low logic) transfers the data in the address or command data

register (depending on the level of RS) onto the data bus.

This is the 8-bit bidirectional data bus for transferring data to and from the SPT2110. The

direction is dictated by the WR_ (input) and RD_ (output) signals.

Refer to the Electrical Specification Table for correct interfacing of the SPT2110. Note the assert times required for each of

the control lines. The times must be a numerical multiple of the clock that operates the SPT2110.

The accessing of a Command register(s) is performed as shown in table VI below.

(Note that 1 defines logic high, 0 is logic low, X is defined as don’t care and D is valid data)

Table VI - Write Address Register

CONT.

STATE\

STEP

1

2

3

4

CS_ WR_ RD_ RS

0

1

1

0

0

0

1

0

0

1

1

0

1

1

1

X

DATA (7-0)

DDh

DDh

DDh

XXh

COMMENTS

Data needs to be valid on the data bus for minimum setup time

(relative to the WR_ signal).

Data needs to remain valid on the data bus for minimum hold

time (relative to the WR_ signal).

Completed Address Write

The address write sequence described above is a normal write sequence. A write can be performed by asserting

CS_ and RS (to logic low). Observe the minimum setup time before asserting WR_. Hold CS_ and RS for the hold

time and then release CS_ and RS. Then set the data bus to the valid address for the minimum setup time before

the rising edge of WR_. Then hold the data bus for the hold time required. Note that the WR_ assert time is a

multiple of the clock. This sequence will perform a valid write to the address register. The following read write

functions may be performed in a manner similar to the normal sequences outlined in the tables VII and VIII.

Table VII - Read Address Register

CONT.

STATE\

STEP

CS_ WR_ RD_ RS

1

0

1

1

0

2

0

1

0

0

3

0

1

1

0

4

1

1

1

X

DATA (7-0)

XXh

DDh

XXh

XXh

COMMENTS

Data is valid on the data bus after output delay time (relative to

the RD_ signal).

Data continues to remain valid for output hold time delay (relative

to the RD_ signal).

Completed Address Read.

SPT

4

SPT2110

3/27/98

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