AD9832(RevA) 데이터 시트보기 (PDF) - Analog Devices
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AD9832 Datasheet PDF : 16 Pages
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AD9832
device. The first bit is read into the device on the next SCLK
falling edge with the remaining bits being read into the device
on the subsequent SCLK falling edges. FSYNC frames the
16 bits, therefore, when 16 SCLK falling edges have occurred,
FSYNC should be taken high again. The SCLK can be continu-
ous or, alternatively, the SCLK can idle high or low between
write operations.
When writing to a frequency/phase register, the first four bits
identify whether a frequency or phase register is being written
to, the next four bits contain the address of the destination
register while the 8 LSBs contain the data. Table II lists the
addresses for the phase/frequency registers while Table III lists
the commands.
Within the AD9832, 16-bit transfers are used when loading the
destination frequency/phase register. There are two modes for
loading a register—direct data transfer and a deferred data
transfer. With a deferred data transfer, the 8-bit word is loaded
into the defer register (8 LSBs or 8 MSBs). However, this data
is not loaded into the 16-bit data register so the destination
register is not updated. With a direct data transfer, the 8-bit
word is loaded into the appropriate defer register (8 LSBs or
8 MSBs). Immediately following the loading of the defer regis-
ter, the contents of the complete defer register are loaded into
the 16-bit data register and the destination register is loaded on
the next MCLK rising edge. When a destination register is
addressed, a deferred transfer is needed first followed by a direct
transfer. When all 16 bits of the defer register contain relevant
data, the destination register can then be updated using 8-bit
loading rather than 16-bit loading i.e., direct data transfers can
be used. For example, after a new 16-bit word has been loaded
to a destination register, the defer register will contain this word
also. If the next write instruction is to the same destination
register, the user can use direct data transfers immediately.
When writing to a phase register, the 4 MSBs of the 16-bit word
loaded into the data register should be zero (the phase registers
are 12 bits wide).
To alter the entire contents of a frequency register, four write
operations are needed. However, the 16 MSBs of a frequency
word are contained in a separate register to the 16 LSBs. There-
fore, the 16 MSBs of the frequency word can be altered inde-
pendent of the 16 LSBs.
The phase and frequency registers to be used are selected using
the pins FSELECT, PSEL0 and PSEL1 or the corresponding
bits can be used. Bit SELSRC determines whether the bits or
the pins are used. When SELSRC = 0, the pins are used while
the bits are used when SELSRC = 1. When CLR is taken high,
SELSRC is set to 0 so that the pins are the default source.
Data transfers from the serial (defer) register to the 16-bit data
register, and the FSELECT and PSEL registers, occur following
the 16th falling SCLK edge. Transfer of the data from the
16-bit data register to the destination register or from the
FSELECT/PSEL register to the respective multiplexer occurs
on the next MCLK rising edge. Since the SCLK and the
MCLK are asynchronous, an MCLK rising edge may occur
while the data bits are in transitional state, which will cause a
brief spurious DAC output if the register being written to is
generating the DAC output. To avoid such spurious outputs,
the AD9832 contains synchronizing circuitry. When the SYNC
bit is set to 1, the synchronizer is enabled and data transfers
from the serial register (defer register) to the 16-bit data register
and the FSELECT/PSEL registers occur following a two stage
pipeline delay which is triggered on the MCLK falling edge.
The pipeline delay ensures that the data is valid when the trans-
fer occurs. Similarly, selection of the frequency/phase registers
using the FSELECT/PSEL pins is synchronized with the
MCLK rising edge when SYNC = 1. When SYNC = 0, the
synchronizer is bypassed.
Selecting the frequency/phase registers using the pins is synchro-
nized with MCLK internally also when SYNC = 1 to ensure
that these inputs are valid at the MCLK rising edge. If times t11
and t11A are met, then the inputs will be at steady state at the
MCLK rising edge. However, if times t11 and t11A are violated,
the internal synchronizing circuitry will delay the instant at
which the pins are sampled, ensuring that the inputs are valid at
the sampling instant.
Associated with each operation is a latency. When inputs
FSELECT/PSEL change value, there will be a pipeline delay
before control is transferred to the selected register—there will
be a pipeline delay before the analog output is controlled by the
selected register. When times t11 and t11A are met, PSEL0,
PSEL1 and FSELECT have latencies of six MCLK cycles when
SYNC = 0. When SYNC = 1, the latency is increased to 8 MCLK
cycles. When times t11 and t11A are not met, the latency can
increase by one MCLK cycle. Similarly, there is a latency asso-
ciated with each write operation. If a selected frequency/phase
register is loaded with a new word, there is a delay of 6 to 7
MCLK cycles before the analog output will change (there is an
uncertainty of one MCLK cycle regarding the MCLK rising
edge at which the data is loaded into the destination register).
When SYNC = 1, the latency will be 8 or 9 MCLK cycles.
The flow chart in Figure 22 shows the operating routine for the
AD9832. When the AD9832 is powered up, the part should be
reset. This will reset the phase accumulator to zero so that the
analog output is at midscale. To avoid spurious DAC outputs
while the AD9832 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high will set SYNC and SELSRC to 0 so that
the FSELECT/PSEL pins are used to select the frequency/
phase registers and the synchronization circuitry is bypassed.
A write operation is needed to the SYNC/SELSRC register to
enable the synchronization circuitry or to change control to
the FSELECT/PSEL bits. RESET does not reset the phase
and frequency registers. These registers will contain invalid
data and, therefore, should be set to a known value by the user.
The RESET bit is then set to 0 to begin generating an output. A
signal will appear at the DAC output 6 MCLK cycles after
RESET is set to 0.
The analog output is fMCLK/232 × FREG where FREG is the
value loaded into the selected frequency register. This signal will
be phase shifted by the amount specified in the selected phase
register (2 π/4096 × PHASEREG where PHASEREG is the
value contained in the selected phase register).
Control of the frequency/phase registers can be interchanged
from the pins to the bits.
REV. A
–11–
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