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SY69952AZC

OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER

Micrel 

Micrel

SY69952A

PIN DESCRIPTIONS

/LOOP – TTL Input

Loop Back Select. This input is used to select the input

data stream source that the Receive PLL uses for clock

and data recovery. When the /LOOP input is HIGH, the

Receive input data stream (RIN±) is used for clock and

data recovery. When /LOOP is LOW, the Transmit input

data stream (TSER±) is used by the Receive PLL for clock

and data recovery. When in Loop-back testing mode, /LOOP

input asserted low, the Receive PLL is always turned-on

internally regardless of the CD input signal level status.

This allows the Recovered Serial Data outputs (RSER±) to

receive data stream from the Transmit serial data inputs

(TSER±).

PLL1±, PLL2± – Loop Filter Inputs

These pins are used to connect the external loop filters

for the two on-board PLLs. See below:

TOP VIEW

MODE – 3 Level Input

Frequency Mode Select. This three-level input selects

the frequency range for the clock and data recovery receive

PLL and the frequency multiplier transmit PLL. When the

input is held PECL HIGH (VCC –0.9 typ.), the two PLLs

operate at the SONET (SDH) STS-3 (STM-1) line rate of

155.52MHz. When this input is held TTL LOW (connected

to GND), the two PLLs operate at one SONET STS-1 line

rate of 51.84MHz. The REFCLK± frequency in both operating

modes is 1⁄8 of the operating frequency. When the MODE

input is ECL LOW (VCC – 1.7 typ), the device enters into

test mode, the TSER± inputs substitue for the internal PLL

VCO for use in factory testing.

Transmit

Filter

0.1µf

500Ω

PLL1+

PLL1-

PLL2+

PLL2-

0.1µf

120Ω

Receiver

Filter

Figure 1. Suggested Loop Filter Values

3

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