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SY69952AZC

OC-3/STS-3 CLOCK RECOVERING TRANSCEIVER

Micrel 

Micrel

SY69952A

DESCRIPTION

General

The SY69952A Transceiver is used in SONET/SDH and

ATM applications to recover clock and data information from

a 155.52MHz or 51.84MHz NRZ (Non Return to Zero) or

NRZI (Non Return to Zero Invert on ones) serial data stream.

This device also provides a bit-rate Transmit clock, from a

byte rate source through the use of a frequency multiplier

PLL, and differential data buffering for the Transmit side of

the system. This device is compliant with all relevant SONET/

SDH specifications including ANSI T1X1.6/91-022, ANSI

T1X1.3/93-006R1 Draft and ITU/CCITT G958.

Operating Frequency

The SY69952A operates at either of two frequency

ranges, the MODE input determines with which of the two

frequencies 51.84MHz or 155.52MHz the Transmit frequency

multiplier PLL, the Receive clock and the data recovery

PLL will operate. When MODE is connected to VCC, the

highest operating range of the device is selected. A

19.44MHz ±1% source must drive the REFCLK input and

the two PLLs will multiply this rate by 8 to provide output

clocks that operate at 155.52MHz ±1%. When the MODE

input is connected to ground (GND), the lowest operating

range of the device is selected. A 6.48MHz ±1% source

must drive the REFCLK inputs and the two PLLs will multiply

this rate by 8 to provide output clocks that operate at

51.84MHz ±1%.

Transmit Functions

The transmit section of the SY69952A contains a PLL

that takes a REFCLK input and multiplies it by 8 (REFCLKx8)

to produce a PECL (Positive ECL) differential output clock

(TCLK±). The transmitter has two operating ranges that are

selectable with the three-level MODE pin as explained above.

The SY69952A Transmit frequency multiplier PLL allows

low-cost byte rate clock sources to be used to time the

upstream serial data transmitter.

The REFCLK± inputs can be configured three ways.

When both REFCLK+ and REFCLK– are connected to a

differential 100K-compatible PECL source, the REFCLK±

inputs will behave as a differential PECL inputs. When either

the REFCLK+ or the REFCLK– input is at a TTL LOW, the

other REFCLK input becomes a TTL–level input allowing it

to be connected to a low-cost TTL crystal oscillator. The

REFCLK± inputs structure, therefore, can be used as a

differential PECL input, a single TTL input, or as a dual TTL

clock multiplexing input.

The Transmit PECL differential input pair (TSER±) is

buffered by the SY69952A yielding the differential data

outputs (TOUT±). These outputs can be used to directly

drive transmission media such as Printed Circuit Board

(PCB) traces, optical drivers, twisted pair, or coaxial cable.

Receive Functions

The primary function of the receiver is to recover clock

(RCLK±) and data (RSER±) from the incoming differential

PECL data stream (RIN±) without the need for external

buffering. These built-in line receiver inputs, as well as the

TSER± inputs mentioned above, have a wide common-

mode range (2.5V) and the ability to receive signals with as

little as 50mV differential voltage. They are compatible with

all PECL signals and any copper media.

The clock recovery function is performed using an

embedded PLL. The recovered clock is not only passed to

the RCLK± outputs, but also used internally to sample the

input serial stream in order to recover the data pattern. The

Receive PLL uses the REFCLK input as a byte-rate

reference. This input is multiplied by 8 (REFCLK × 8) and is

used to improve PLL lock time and to provide a center

frequency for operation in the absence of input data stream

transitions. The receiver can recover clock and data in two

different frequency ranges depending on the state of the

MODE pin as explained earlier. To insure accurate data

and clock recovery, REFCLK × 8 must be within 1000ppm

of the transmit bit rate. The standards, however, specify

that the REFCLK × 8 frequency accuracy be within 20-

100ppm.

The differential input serial data (RIN±) is not only used

by the PLL to recover the clock and data, but it is also

buffered and presented as the PECL differential output pair

ROUT±. This output pair can be used as part of the

transmission line interface circuit for base line wander

compensation, improving system performance by providing

reduced input jitter and increased data eye opening.

Carrier Detect and Link Fault Indicator Functions

The Link Fault Indicator (/LFI) output is a TTL–level output

that indicates the status of the receiver. This output can be

used by an external controller for Loss of Signal (LOS),

Loss of Frame (LOF), or Out of Frame (OOF) indications.

/LFI is controlled by the Carrier Detect input, the internal

Transitions Detector, and the PLL Out of Lock (OOL)

circuitry.

The CD input may be driven by external circuitry that is

monitoring the incoming data stream. Optical modules have

CD outputs that indicate the presence of light on the optical

fiber and some copper based systems use external threshold

detection circuitry to monitor the incoming data stream. The

CD input is a 100K PECL compatible signal that should be

held HIGH when the incoming data stream is valid. When

CD is pulled to a PECL LOW (≤2.5V max.), the /LFI output

will transition LOW except in the loopback mode, and the

Receiver PLL will align itself with the REFCLKx8 frequency

and the recovered data outputs (RSER±) will remain LOW

regardless of the signal level on the Receive data-stream

inputs (RIN±).

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