74F273AD 데이터 시트보기 (PDF) - Philips Electronics
부품명
상세내역
제조사
74F273AD Datasheet PDF : 10 Pages
| |||
Philips Semiconductors
Octal D flip–flop
Product specification
74F273A
FEATURES
• High impedance inputs for reduced loading
(20µA in Low and High states)
• Ideal buffer for MOS microprocessor or memory
• Eight edge–triggered D–type flip–flops
• Buffered common clock
• Buffered asynchronous Master Reset
• See 74F377A for clock enable version
• See 74F373 for transparent latch version
• See 74F374 for 3–State version
DESCRIPTION
The 74F273 has eight edge–triggered D–type flip–flops with
individual D inputs and Q outputs. The common buffered Clock (CP)
and Master Reset (MR) inputs load and reset (clear) all flip–flops
simultaneously.
The register is fully edge–triggered. The state of each D input, one
setup time before the Low–to–High clock transition, is transferred to
the corresponding flip–flop’s Q output.
All outputs will be forced Low independently of Clock or Data inputs
by a Low voltage level on the MR input. The device is useful for
applications where the true output only is required and the CP and
MR are common to all elements.
TYPE
74F273A
TYPICAL
fMAX
170MHz
TYPICAL SUPPLY CURRENT
(TOTAL)
25mA
ORDERING INFORMATION
PACKAGES
COMMERCIAL RANGE
VCC = 5V±10%;
Tamb = 0°C to +70°C
PKG. DWG. #
20–pin plastic DIP
74F273AN
SOT146-1
20–pin plastic SOL
74F273AD
SOT163-1
INPUT AND OUTPUT LOADING AND FAN-OUT TABLE
PINS
DESCRIPTION
D0 – D7
MR
CP
Q0 – Q7
Data inputs
Master Reset input (active–Low)
Clock pulse input (active rising edge)
Data outputs
74F(U.L.)
HIGH/LOW
1.0/0.033
1.0/0.033
1.0/0.033
50/33
LOAD VALUE
HIGH/LOW
20µA/20µA
20µA/20µA
20µA/20µA
1.0mA/20mA
PIN CONFIGURATION
MR 1
Q0 2
D0 3
D1 4
Q1 5
Q2 6
D2 7
D3 8
Q3 9
GND 10
20 VCC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CP
SF00346
LOGIC SYMBOL
3 4 7 8 13 14 17 18
D0 D1 D2 D3 D4 D5 D6 D7
11
CP
1
MR
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
VCC = Pin 20
GND = Pin 10
2 5 6 9 12 15 16 19
SF00347
1996 Mar 12
2
853–0066 16555
Share Link: 