SN74LS273DW 데이터 시트보기 (PDF) - Motorola => Freescale
부품명
상세내역
제조사
SN74LS273DW Datasheet PDF : 5 Pages
| |||
SN54 / 74LS273
AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V)
Limits
Symbol
Parameter
Min Typ Max Unit
tw
Pulse Width, Clock or Clear
20
ns
ts
Data Setup Time
20
ns
th
Hold Time
5.0
ns
trec
Recovery Time
25
ns
Test Conditions
Figure 1
Figure 1
Figure 1
Figure 2
AC WAVEFORMS
CP
D
Qn
1.3 V
1.3 V
1/f max
tW
1.3 V
1.3 V
ts(H)
*
1.3 V
th(H)
ts(L)
tPLH
1.3 V
1.3 V
th(L)
1.3 V
tPHL
1.3 V
tPHL
tPLH
*The shaded areas indicate when the input is permitted to
*change for predictable output performance.
Figure 1. Clock to Output Delays, Clock Pulse Width,
Frequency, Setup and Hold Times Data to Clock
MR
tW
1.3 V
CP
Qn
tPLH
Qn
tPHL
1.3 V
1.3 V
trec
1.3 V
1.3 V
1.3 V
Figure 2. Master Reset to Output Delay, Master Reset
Pulse Width, and Master Reset Recovery Time
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required
for the correct logic level to be present at the logic input prior to
the clock transition from LOW-to-HIGH in order to be recog-
nized and transferred to the outputs.
HOLD TIME (th) — is defined as the minimum time following
the clock transition from LOW-to-HIGH that the logic level
must be maintained at the input in order to ensure continued
recognition. A negative HOLD TIME indicates that the correct
logic level may be released prior to the clock transition from
LOW-to-HIGH and still be recognized.
RECOVERY TIME (trec) — is defined as the minimum time
required between the end of the reset pulse and the clock
transition from LOW-to-HIGH in order to recognize and
transfer HIGH data to the Q outputs.
FAST AND LS TTL DATA
5-449
Share Link: 