SN74LS273ML2 데이터 시트보기 (PDF) - ON Semiconductor

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SN74LS273ML2

Octal D Flip-Flop with Clear

ON Semiconductor 

SN74LS273

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP

20 19 18 17 16 15 14 13 12 11

1 2 3 4 5 6 7 8 9 10

MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND

PIN NAMES

CP

D0 - D7

MR

Q0 - Q7

Clock (Active HIGH Going Edge) Input

Data Inputs

Master Reset (Active LOW) Input

Register Outputs

NOTES:

ąa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

3

11

D0

CP

CP D

1

CD Q

MR

VCC = PIN 20

GND = PIN 10

= PIN NUMBERS

Q0

2

4

D1

CP D

CD Q

Q1

5

TRUTH TABLE

MR CP Dx Qx

LXX L

H

HH

H

L

L

H = HIGH Logic Level

L = LOW Logic Level

X = Immaterial

LOGIC DIAGRAM

7

8

13

D2

D3

D4

CP D

CD Q

CP D

CD Q

CP D

CD Q

14

D5

CP D

CD Q

Q2

Q3

Q4

Q5

6

9

12

15

17

D6

CP D

CD Q

Q6

16

18

D7

CP D

CD Q

Q7

19

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