SN74LS273ML2 데이터 시트보기 (PDF) - ON Semiconductor

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SN74LS273ML2

Octal D Flip-Flop with Clear

ON Semiconductor 

SN74LS273

AC WAVEFORMS

1/f max

tW

CP

1.3 V

1.3 V

1.3 V

1.3 V

ts(H)

th(H) ts(L)

th(L)

D

*

1.3 V

1.3 V 1.3 V

tPLH

tPHL

Qn

1.3 V

1.3 V

tPHL

tPLH

*The shaded areas indicate when the input is permitted to

*change for predictable output performance.

Figure 1. Clock to Output Delays, Clock Pulse Width,

Frequency, Setup and Hold Times Data to Clock

DEFINITION OF TERMS

SETUP TIME (ts) — is defined as the minimum time

required for the correct logic level to be present at the logic

input prior to the clock transition from LOW-to-HIGH in

order to be recognized and transferred to the outputs.

HOLD TIME (th) — is defined as the minimum time

following the clock transition from LOW-to-HIGH that the

logic level must be maintained at the input in order to ensure

MR

tW

1.3 V

CP

tPHL

Qn

1.3 V

tPLH

Qn

1.3 V

trec

1.3 V

1.3 V

1.3 V

Figure 2. Master Reset to Output Delay, Master Reset

Pulse Width, and Master Reset Recovery Time

continued recognition. A negative HOLD TIME indicates

that the correct logic level may be released prior to the clock

transition from LOW-to-HIGH and still be recognized.

RECOVERY TIME (trec) — is defined as the minimum time

required between the end of the reset pulse and the clock

transition from LOW-to-HIGH in order to recognize and

transfer HIGH data to the Q outputs.

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