MTV118 데이터 시트보기 (PDF) - Myson Century Inc

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MTV118

On-Screen-Display for LCD Monitor

Myson Century Inc 

MYSON

TECHNOLOGY

MTV118

b7 b6 B5 b4 b3 b2 b1 b0

Column 16 -

-

-

RSPACE

MSB

LSB

RSPACE - Defines the row to row spacing in each unit of the horizontal line. That is, extra RSPACE

horizontal lines will be appended below each display row, and the maximum space is 31

lines. The initial value is “0” after power-up.

Column 17

b7

OSDEN

b6

BSEN

b5

SHADOW

b4

TRIC

b3

BLANK

b2

WENCLR

b1

RAMCLR

b0

FBKGC

OSDEN - Activates the OSD operation when this bit is set to "1". The initial value is” 0” after power-up.

BSEN - Enables the bordering and shadowing effect.

SHADOW - Activates the shadowing effect if this bit is set, otherwise the bordering is chosen.

TRIC - Defines the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled.

That is, while OSD is disabled, these 4 pins will drive LOW if this bit is set to “1”, otherwise these

pins are in high-impedance state. The initial value is “0” after power-up.

BLANK - Forces the FBKG pin output to HIGH while this bit is set to "1".

WENCLR - Clears all WEN bits of window control registers when this bit is set to "1". The initial value is

“0” after power-up.

RAMCLR - Clears all ADDRESS bytes of display registers when this bit is set to "1". The initial value is

“0” after power-up.

FBKGC - Defines the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during

the display of characters or windows, otherwise, it outputs only during the display of charac-

ters.

Column 18

B7

TEST

b6

b5

FBKGP PWMCK

b4

DWE

b3

HSP

TEST - = 0 ⇒ Normal mode.

= 1 ⇒ Test mode, not allowed in applications.

b2

b1

b0

VSP PWM1 PWM0

FBKGP - Selects the polarity of the output pin FBKG.

= 1 ⇒Positive polarity FBKG output is selected.

= 0 ⇒Negative polarity FBKG output is selected.

The initial value is “1” after power-up.

PWMCK - Selects the output options to the HTONE/PWMCK pin.

= 0 ⇒? HTONE option is selected.

= 1 ⇒? PWMCK option is selected with 50/50 duty cycle and is synchronous with the input

HFLB. The frequency is selected by PWM1, PWM0 as shown in table 4.

The initial value is “0” after power-up.

DWE - Enables double width. When the bit is set to “1”, the display of the OSD menu can change to half

resolution for double character width, and then the number of pixels of each line should be even.

HSP - = 1 ⇒ Accepts positive polarity Hsync input.

10/15

MTV118 Revision 2.0 01/01/1999

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