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OR3LP26B

ORCA® OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Agere -> LSI Corporation 

Data Sheet

March 2000

ORCA OR3LP26B FPSC

Embedded Master/Target PCI Interface

Contents

Table of Contents (continued)

Page Contents

Page

Figure 10. Target Configuration Write

(PCI Bus, 64-Bit) ...........................................................52

Figure 11. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...53

Figure 12. Target Write Memory Single

(PCI Bus, 64-Bit) ...........................................................54

Figure 13. Target Write Single (FPGA Bus, Dual-Port)....55

Figure 14. Target Memory Write 32-Byte Burst

(PCI Bus, 64-Bit) ...........................................................56

Figure 15. Target Write Memory 32-Byte Burst

(FPGA Bus, Dual-Port) .................................................57

Figure 16. Target Configuration Read

(PCI Bus, 64-Bit) ...........................................................61

Figure 17. Target I/O Read, Delayed (PCI Bus, 64-Bit) ...62

Figure 18. Target I/O Read, Not Delayed

(PCI Bus, 64-Bit) ...........................................................63

Figure 19. Target Memory Single Read, Delayed

(PCI Bus, 64-Bit) ...........................................................64

Figure 20. Target Read Single (FPGA Bus, Dual-Port)....65

Figure 21. Target Memory Read Single, Not Delayed

(PCI Bus, 64-Bit) ...........................................................66

Figure 22. Target Memory Read 32-Byte Burst, Delayed

(PCI Bus, 64-Bit) ...........................................................67

Figure 23. Target Read Memory 32-Byte Burst

(FPGA, Dual-Port) ........................................................68

Figure 24. Target Read Memory Burst, No Delayed

(PCI Bus, 32-Bit) ...........................................................69

Figure 25. Master Write Single (PCI Bus, 64-Bit) ............90

Figure 26. Master Write 32-Byte Burst

(PCI Bus, 64-Bit) ...........................................................91

Figure 27. Master Write Single Quadword

(FPGA Bus, Quad-Port, 64-Bit Address) ......................92

Figure 28. Master Write 32-Byte Burst

(FPGA Bus, Quad-Port, 64-Bit Address) ......................93

Figure 29. Master Read Single (PCI Bus, 64-Bit) ............96

Figure 30. Master Read Single Quadword (FPGA Bus,

Quad-Port, Specified Burst Length, 32-Bit Address) ....97

Figure 31. Master Read 32-Byte Burst

(PCI Bus, 64-Bit) ...........................................................98

Figure 32. Master Read 32-Byte Burst (FPGA Bus,

Quad-Port, Specified Burst Length, 32-Bit Address) ....99

Figure 33. Target Configuration Write

(PCI Bus, 64-Bit) ...........................................................104

Figure 34. Target I/O Write, Delayed (PCI Bus, 64-Bit) ...105

Figure 35. Target Write Memory Single

(PCI Bus, 64-Bit) ...........................................................106

Figure 36. Target Write Single Quadword

(FPGA Bus, Quad-Port, 64-Bit Address) ......................107

Figure 37. Target Memory Write 32-Byte Burst

(PCI Bus, 64-Bit) ...........................................................108

Figure 38. Target Write Memory 32-Byte Burst

(FPGA Bus, Quad-Port, 32-Bit Address) ......................109

Figure 39. Target Configuration Read

(PCI Bus, 64-Bit) ...........................................................113

Figure 40. Target I/O Read, Delayed

(PCI Bus, 64-Bit) ...........................................................114

Figure 41. Target I/O Read, Not Delayed

(PCI Bus, 64-Bit) .......................................................... 115

Figure 42. Target Memory Single Read, Delayed

(PCI Bus, 64-Bit) .......................................................... 116

Figure 43. Target Read Single (FPGA Bus, Quad-Port,

64-Bit Address)............................................................. 117

Figure 44. Target Memory Read Single, Not Delayed

(PCI Bus, 64-Bit) .......................................................... 118

Figure 45. Target Memory Read 32-Byte Burst, Delayed

(PCI Bus, 64-Bit) .......................................................... 119

Figure 46. Target Read Memory 32-Byte Burst

(FPGA Bus, Quad-Port, 32-Bit Address) ...................... 120

Figure 47. Target Read Memory Burst, No Delayed

(PCI Bus, 32-Bit) .......................................................... 121

Figure 48. FPSC Block Diagram and Clock Network ...... 129

Figure 49. Serial Configuration Data Format—

Autoincrement Mode .................................................... 131

Figure 50. Serial Configuration Data Format—

Explicit Mode ................................................................ 131

Figure 51. ExpressCLK to Output Delay ......................... 138

Figure 52. Fast Clock to Output Delay ............................ 139

Figure 53. System Clock to Output Delay ....................... 140

Figure 54. Input to ExpressCLK Setup/Hold Time .......... 141

Figure 55. Input to Fast Clock Setup/Hold Time.............. 142

Figure 56. Input to System Clock Setup/Hold Time ........ 143

Figure 57. ac Test Loads ................................................. 148

Figure 58. Output Buffer Delays ...................................... 148

Figure 59. Input Buffer Delays......................................... 148

Figure 60. Sinklim (TJ = 25 °C, VDD = 3.3 V) ................. 149

Figure 61. Slewlim (TJ = 25 °C, VDD = 3.3 V) ................ 149

Figure 62. Fast (TJ = 25 °C, VDD = 3.3 V)...................... 149

Figure 63. Sinklim (TJ = 125 °C, VDD = 3.0 V) ............... 149

Figure 64. Slewlim (TJ = 125 °C, VDD = 3.0 V) .............. 149

Figure 65. Fast (TJ = 125 °C, VDD = 3.0 V).................... 149

Figure 66. Package Parasitics ......................................... 180

Tables

Table 1. ORCA OR3LP26B PCI FPSC Solution—

Available FPGA Logic................................................... 1

Table 2. PCI Local Bus Data Rates ................................ 10

Table 3. OR3LP26B Array .............................................. 11

Table 4. PCI Bus Command Descriptions ...................... 14

Table 5. Timing Budgets................................................. 17

Table 6. FIFO Flags Provided to FPGA Application ....... 18

Table 7. PCI Bus Pin Descriptions.................................. 18

Table 8. Embedded Core/FPGA Interface Signals ......... 21

Table 9. OR3LP26B FPGA/PCI Core Interface Signal

Locations ...................................................................... 27

Table 10. Bit Definitions on FPGA/PCI Core Interface ... 30

Table 11. Address Cycle Sequences for Various

Operations ................................................................... 31

Table 12. PCI Core Options Settable via FPGA

Configuration RAM Bits ................................................ 32

Lucent Technologies Inc.

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Lucent Technologies Inc.

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