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OR3LP26B

ORCA® OR3LP26B Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface

Agere -> LSI Corporation 

ORCA OR3LP26B FPSC

Embedded Master/Target PCI Interface

Data Sheet

March 2000

FPSC Highlights (continued)

— Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU.

— Supplemental logic and interconnect cell (SLIC)

provides 3-statable buffers, up to 10-bit decoder,

and PAL*-like AND-OR-INVERT (AOI) in each

programmable logic cell (PLC).

— Up to three ExpressCLK inputs allow extremely

fast clocking of signals on- and off-chip plus

access to internal general clock routing.

— Dual-use microprocessor interface (MPI) can be

used for configuration, readback, device control,

and device status, as well as for a general-pur-

pose interface to the FPGA. Glueless interface to

i960† and PowerPC ‡ processors with user-config-

urable address space provided.

— Programmable clock manager (PCM) adjusts

clock phase and duty cycle for input clock rates

from 5 MHz to 120 MHz. The PCM may be com-

bined with FPGA logic to create complex func-

tions, such as digital phase-locked loops (DPLL),

frequency counters, and frequency synthesizers

or clock doublers. Two PCMs are provided per

device.

— True internal 3-state, bidirectional buses with sim-

ple control provided by the SLIC.

— 32 x 4 RAM per PFU, configurable as single or

dual port. Create large, fast RAM/ROM blocks

(128 x 8 in only eight PFUs) using the SLIC

decoders as bank drivers.

— Built-in boundary scan (IEEE §1149.1 JTAG) and

TS_ALL testability function to 3-state all I/O pins.

s High-speed on-chip interface provided between

FPGA logic and embedded core to reduce bottle-

necks typically found when interfacing off-chip.

s Supported in two packages: 352-pin PBGA and

680-pin PBGAM.

Note: This document will conform to the nomenclature

of the PCI Local Bus Specification, as follows:

Term

byte

word

DWORD

Quadword

Meaning

8 bits

16 bits

32 bits

64 bits

Software Support

s Supported by ORCA Foundry software and third-

party CAE tools for implementing ORCA Series 3+

devices and simulation/timing analysis with embed-

ded PCI bus core.

s PCI core configuration options and simulation

netlists generated by FPSC Configuration Manager

utility in ORCA Foundry software.

s Preference files provided for timing interface between

PCI bus core and FPGA logic.

* PAL is a trademark of Advanced Micro Devices, Inc.

† i960 is a registered trademark of Intel Corporation.

‡ PowerPC is a registered trademark of International Business

Machines Corporation.

§ IEEE is a registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

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