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ORT82G5

ORCA® ORT82G5 1.0—1.25/2.0—2.5/3.125 Gbits/s Backplane Interface FPSC

Agere -> LSI Corporation 

ORCA ORT82G5 FPSC Eight-Channel

1.0-1.25/2.0-2.5/3.125 Gbits/s Backplane Interface

Preliminary Data Sheet

July 2001

Embedded Function Features

s High-speed SERDES programmable serial data

rates of 622 Mbits/s (SONET only), 1.25 Gbits/s,

2.5 Gbits/s, and 3.125 Gbits/s.

s Asynchronous operation per receive channel with the

receiver frequency tolerance based on one reference

clock per quad channels (separate PLL per channel).

s Ability to select full-rate or half-rate operation per Tx

or Rx channel by setting the appropriate control reg-

isters.

s Transmit preemphasis (programmable) for improved

receive data eye opening.

s Receiver energy detector to determine if a link is

active.

s 32-bit (SONET or 8b/10b) or 40-bit (raw data) paral-

lel internal bus for data processing in FPGA logic.

s Provides a 10 Gbits/s backplane interface to switch

fabric with protection. Also supports port cards at

622 Mbits/s or 2.5 Gbits/s.

s 3.125 Gbits/s SERDES compliant with XAUI serial

data specification for 10 Gbit Ethernet applications

with protection.

s Most XAUI features for 10 Gbit Ethernet are embed-

ded including the required link state machine.

s Compliant to fibre-channel physical layer specifica-

tion.

s Allows wide range of applications for SONET net-

work termination, as well as generic data moving for

high-speed backplane data transfer.

s No knowledge of SONET/SDH needed in generic

applications. Simply supply data, a 100 MHz—

156.25 MHz reference clock, and, optionally, a frame

pulse.

s High-speed interface (HSI) function for clock/data

recovery serial backplane data transfer without exter-

nal clocks.

s Eight-channel HSI function provides 2.5 Gbits/s

serial user data interface per channel for a total chip

bandwidth of 20 Gbits/s (full duplex).

s SERDES has low-power CML buffers. Support for

1.5 V/1.8 V I/Os.

s Programmable STS-12 or STS-48 framing in SONET

mode per channel (in version II). OC-192 framing in

quad OC-48 (four channels) also supported.

s Powerdown option of SERDES HSI receiver on a

per-channel basis.

s Selectable 8b/10b coder/decoder or SONET scram-

bler/descrambler (added for version 2).

4

s SERDES HSI automatically recovers from loss-of-

clock once its reference clock returns to normal oper-

ating state.

s In-band management and configuration through

transport overhead extraction/insertion in SONET

mode (version II).

s Supports transparent mode where the only insertion

is A1/A2 framing bytes in SONET mode (version II).

s Built-in boundary scan (IEEE ® 1149.1 and 1149.2

JTAG) for the programmable I/Os, not including the

SERDES interface.

s FIFOs align incoming data across all eight channels

(all eight channels, two groups of four channels, or

four groups of two channels). Alignment is done

using comma characters or /A/ in 8b/10b mode or

frame pulse in SONET mode (version II). Optional

ability to bypass alignment FIFOs for asynchronous

operation between channels. (Each channel includes

its own clock and frame pulse or comma detect.)

s Frame alignment across multiple ORT82G5 devices

for work/protect switching at STS-768/STM256 and

above rates in SONET mode.

s Addition of two 4K X 36 dual-port RAMs with access

to the programmable logic.

Intellectual Property Features

Programmable logic provides a variety of yet-to-be

standardized interface functions, including the following

Agere ME IP core functions:

s 10 Gbits/s Ethernet as defined by IEEE 802.3ae:

— XGMII for interfacing to 10 Gbits/s Ethernet

MACs. XGMII is a 156 MHz double data rate par-

allel short reach (typically less than 2") intercon-

nect interface.

— X58+ X39 + X1 scrambler/descrambler for

10 Gbits/s Ethernet.

— 64b/66b encoders/decoders for 10 Gbits/s Ether-

net.

— XAUI to XGMII translator, including dual XAUI pro-

tection.

s POS-PHY4 interface for 10 Gbits/s SONET/SDH and

OTN systems and some 10 Gbits/s Ethernet systems

to allow easy integration of InfiniBand, fibre-channel,

and 10 Gbits/s Ethernet in data over fibre applica-

tions.

s Ethernet MAC functions at 10/100 Mbits/s, 1 Gbits/s,

and 10 Gbits/s.

s Other functions such as fibre-channel and InfiniBand

link layer IP cores are also going to be developed.

Agere Systems Inc.

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