UCB1500 데이터 시트보기 (PDF) - Philips Electronics
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UCB1500 Datasheet PDF : 58 Pages
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Philips Semiconductors
UCB1500
PCI to AC97 bridge/host controller
Table 2: Pin description…continued
Symbol
Pin
Type
IRDY
30
S/T/S
TRDY
31
S/T/S
DEVSEL
33
S/T/S
STOP
34
S/T/S
IDSEL
15
I
AD[31:0]
4, 5, 7, 8, 9, 10, 12, T/S
13, 17, 18, 19, 20,
23, 24, 25, 26,41,
42, 44, 45, 46, 47,
49, 50, 52, 54, 55,
56, 57, 59, 60, 62
CBE[3:0]
14, 28, 39, 51
T/S
PAR
38
T/S
INTA
77
O/D [2]
PME
63
O/D
SERR
36
PERR
35
CLKRUN
78
O/D
S/T/S
S/T/S
AC link controller interface
BITCLK
75
I
SDATAIN[1:0] 65. 64
I
SDATAOUT 70
O
SYNC
71
O
AC97_RST 66
O
Serial EEPROM interface
EEPCLK
73
O
EEPD
74
I/O
Power management; miscellaneous
VAUX_AV
69
I
TEST
79
I
Power pins
VDD
1, 11, 22, 27, 37, S
43, 53, 61
VSS
6, 16, 21, 32, 40, S
48, 58, 72, 76
VAUX
67
S
Description
PCI IRDY, input during slave, output during master.
PCI TRDY, output during slave, input during master.
PCI DEVSEL, output during slave, input during master.
PCI STOP, output during slave, input during master.
PCI IDSEL signal.
PCI address/data.
slave mode: output only during data read phase.
master mode: output during address phase and data write phase.
PCI command/byte-enable, input during slave, output during master.
PCI parity.
PCI interrupt.
Open drain, VAUX powered PCI power management pin. SDA TAIN[1:0]
pins are VAUX powered and can trigger PME.
PCI system error
PCI parity error
Primary PCI bus clock run. Used by the central resource to stop the PCI
clock or to slow it down
Serial data clock; or input for secondary codecs.
Input from AC97/MC97 codecs. VAUX powered and can trigger PME.
Output to AC97/MC97 codecs. Driven to 0 at power-up or when RST
asserted.
AC97 sync. Driven to 0 at power-up or when RST asserted.
AC97 reset. Driven to 0 at power-up or when RST asserted. VAUX powered.
EEPROM clock.
EEPROM serial data port.
Auxiliary power available, VAUX powered.
Test mode.
3.3 V power pins.
Ground pins.
Auxiliary power. If auxiliary power is not available or not necessary, this pin
must be connected to VDD.
[1] S/T/S: Sustained Tri-State is an active-LOW tri-state signal owned and driven by one agent at a time. The agent that drives an S/T/S pin
LOW must drive it HIGH for at least one clock before letting it float. A new agent cannot start driving a S/T/S signal any sooner than one
clock after the previous owner tri-states it.
[2] O/D: Open Drain allows multiple devices to share as a wired OR.
9397 750 06854
Objective specification
Rev. 01 — 4 February 2000
© Philips Electronics N.V. 2000. All rights reserved.
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