82371AB 데이터 시트보기 (PDF) - Intel
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82371AB Datasheet PDF : 284 Pages
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82371AB (PIIX4)
11.4. Suspend/Resume and Power Plane Control ..........................................................................................228
11.4.1. System Suspend..............................................................................................................................228
11.4.2. System Resume ..............................................................................................................................230
11.4.3. System Suspend and Resume Control Signaling............................................................................232
11.4.3.1. Power Supply Timings ..............................................................................................................232
11.4.3.2. Power Level Active Status Signal Timings ...............................................................................233
11.4.3.3. Power Management Signal Timings (Powered From Suspend Power Well) ...........................234
11.4.3.4. PCI Clock Stop and Start Timing Relationships .......................................................................235
11.4.3.5. Power Management Signal Timings (Powered From PIIX4 Main Core Well) ..........................236
11.4.3.6. Power Management Signal Timings (Powered From PIIX4 Main Core Well) ..........................238
11.4.3.7. Mechanical Off to On Condition Timings ..................................................................................240
11.4.3.8. On State to Power On Suspend State Timing ..........................................................................242
11.4.3.9. Power On Suspend to On Timing (With a Full System Reset).................................................244
11.4.3.10. System Transition From Power On Suspend to On (With Only Processor Reset)................246
11.4.3.11. Power On Suspend to On Timing (With No Resets) ..............................................................248
11.4.3.12. On State to Suspend to RAM State Timing ............................................................................250
11.4.3.13. Suspend-To-RAM to On Timing (With Full System Reset) ....................................................252
11.4.3.14. On State to Suspend to Disk/Soft Off State Timings..............................................................254
11.4.3.15. Suspend-To-Disk to On (With Full System Reset).................................................................256
11.4.4. Shadow Registers............................................................................................................................258
11.5. System Management..............................................................................................................................262
11.5.1. SMI Operation..................................................................................................................................262
11.5.2. SMI# Generation Events..................................................................................................................263
11.5.3. Global Standby Timer Operation .....................................................................................................265
11.5.4. SMBus Functional Description ........................................................................................................266
11.5.4.1. SMBus Host Interface...............................................................................................................266
11.5.4.2. SMBus Slave Interface .............................................................................................................267
11.6. ACPI Support..........................................................................................................................................268
11.6.1. SCI Generation ................................................................................................................................268
11.6.2. Power Management Timer...............................................................................................................268
11.6.3. Global Lock......................................................................................................................................269
12.0. PINOUT INFORMATION ...........................................................................................................................270
13.0. PIIX4 PACKAGE INFORMATION.............................................................................................................274
14.0. TESTABILITY ............................................................................................................................................277
14.1. Test Mode Description............................................................................................................................277
14.2. Tri-state Mode.........................................................................................................................................278
14.3. NAND Tree Mode ...................................................................................................................................278
PRELIMINARY
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4/9/97 2:23 PM PIIX4aDS
INTEL CONFIDENTIAL
(until publication date)
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