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82371AB

PCI-TO-ISA / IDE XCELERATOR (PIIX4)

Intel 

E

82371AB (PIIX4)

8.1.1. I/O Accesses .....................................................................................................................................154

8.1.2. Memory Address Map........................................................................................................................154

8.1.3. BIOS Memory ....................................................................................................................................155

8.2. PCI Interface.............................................................................................................................................157

8.2.1. Transaction Termination ....................................................................................................................157

8.2.2. Parity Support ....................................................................................................................................157

8.2.3. PCI Arbitration....................................................................................................................................157

8.3. ISA/EIO Interface......................................................................................................................................158

8.4. DMA Controller .........................................................................................................................................158

8.4.1. DMA Transfer Modes.........................................................................................................................159

8.4.2. DMA Transfer Types .........................................................................................................................160

8.4.3. DMA Timings .....................................................................................................................................161

8.4.4. DMA Buffer for Type F Transfers ......................................................................................................161

8.4.5. DREQ and DACK# Latency Control..................................................................................................161

8.4.6. Channel Priority .................................................................................................................................162

8.4.7. Register Functionality ........................................................................................................................162

8.4.8. Address Compatibility Mode ..............................................................................................................162

8.4.9. Summary of DMA Transfer Sizes......................................................................................................163

8.4.9.1. Address Shifting When Programmed for 16-Bit I/O Count by Words.........................................163

8.4.10. Autoinitialize.....................................................................................................................................163

8.4.11. Software Commands .......................................................................................................................164

8.4.12. ISA Refresh Cycles .........................................................................................................................164

8.5. PCI DMA...................................................................................................................................................165

8.5.1. PC/PCI DMA......................................................................................................................................165

8.5.2. Distributed DMA.................................................................................................................................168

8.6. Interrupt Controller ....................................................................................................................................171

8.6.1. Programming the Interrupt Controller ................................................................................................172

8.6.2. End-of-Interrupt Operation.................................................................................................................173

8.6.3. Modes of Operation ...........................................................................................................................173

8.6.4. Cascade Mode...................................................................................................................................175

8.6.5. Edge and Level Triggered Mode........................................................................................................175

8.6.6. Interrupt Masks ..................................................................................................................................176

8.6.7. Reading the Interrupt Controller Status .............................................................................................176

8.6.8. Interrupt Steering ...............................................................................................................................177

8.7. Serial Interrupts.........................................................................................................................................178

8.7.1. Protocol..............................................................................................................................................178

8.8. Timer/Counters .........................................................................................................................................180

8.8.1. Programming the Interval Timer ........................................................................................................180

8.9. Real Time Clock .......................................................................................................................................183

8.9.1. RTC Registers and RAM ...................................................................................................................183

8.9.1.1. Control Register A.......................................................................................................................185

8.9.1.2. Control Register B.......................................................................................................................186

8.9.1.3. Control Register C ......................................................................................................................187

PRELIMINARY

9

4/9/97 2:23 PM PIIX4aDS

INTEL CONFIDENTIAL

(until publication date)

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