QL3012-0PL84C(1999) 데이터 시트보기 (PDF) - QuickLogic Corporation

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QL3012-0PL84C
(Rev.:1999)

12,000 Usable PLD Gate pASIC®3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

pASIC 3

HIGHLIGHTS

… 12,000

usable PLD gates,

118 I/O pins

QL3012

12,000 Usable PLD Gate pASIC®3 FPGA

Combining High Performance and High Density

April, 1999

High Performance and High Density

-12,000 Usable PLD Gates with 118 I/Os

-16-bit counter speeds over 300 MHz, data path speeds over 400 MHz

-0.35µm four-layer metal non-volatile CMOS process for smallest die sizes

4

pASIC 3

Easy to Use / Fast Development Cycles

-100% routable with 100% utilization and complete pin-out stability

-Variable-grain logic cells provide high performance and 100% utilization

-Comprehensive design tools include high quality Verilog/VHDL synthesis

Advanced I/O Capabilities

-Interfaces with both 3.3 volt and 5.0 volt devices

-PCI compliant with 3.3V and 5.0V buses for -1/-2/-3/-4 speed grades

-Full JTAG boundary scan

-Registered I/O cells with individually controlled clocks and output enables

QL3012

Block Diagram

320

Logic

Cells

4-17

QL3012-rev. B

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