QL3012-0PL84C(1999) 데이터 시트보기 (PDF) - QuickLogic Corporation

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QL3012-0PL84C
(Rev.:1999)

12,000 Usable PLD Gate pASIC®3 FPGA Combining High Performance and High Density

QuickLogic Corporation 

QL3012

PRODUCT

SUMMARY

The QL3012 is a 12,000 usable PLD gate member of the pASIC 3 family of

FPGAs. pASIC 3 FPGAs are fabricated on a 0.35µm four-layer metal process

using QuickLogic’s patented ViaLink technology to provide a unique

combination of high performance, high density, low cost, and extreme ease-of-

use.

The QL3012 contains 320 logic cells. With a maximum of 118 I/Os, the

QL3012 is available in 84-pin PLCC, 100-pin TQFP, and 144-pin TQFP

packages.

Software support for the complete pASIC 3 family, including the QL3012, is

available through three basic packages. The turnkey QuickWorks® package

provides the most complete FPGA software solution from design entry to logic

synthesis, to place and route, to simulation. The QuickWorks-LiteTM and

QuickToolsTM packages provide a solution for designers who use Cadence,

Exemplar, Mentor, Synopsys, Synplicity, Viewlogic, Veribest, or other third-

party tools for design entry, synthesis, or simulation.

Total of 118 I/O Pins

- 110 bidirectional input/output pins, PCI-compliant for

5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades

- 4 high-drive input-only pins

- 4 high-drive input/distributed network pins

Four Low-Skew Distributed Networks

- Two array clock/control networks available to the logic cell flip-flop

clock, set and reset inputs - each driven by an input-only pin

- Two global clock/control networks available to the logic cell F1, clock,

set and reset inputs and the input and I/O register clock, reset and enable

inputs as well as the output enable control - each driven by an input-only

or I/O pin, or any logic cell output or I/O cell feedback

High Performance

- Input + logic cell + output total delays under 6 ns

- Data path speeds over 400 MHz

- Counter speeds over 300 MHz

4-25

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