PI6C106 데이터 시트보기 (PDF) - Pericom Semiconductor

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PI6C106

Pentium/ProTM System Clock Chip

Pericom Semiconductor 

PI6C106

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CPU_STOP# Timing Diagram

CPUS_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.

All other clocks will continue to run while the CPUCLKs clocks are disabled.

The CPUCLKs will always be stopped in a low state and start in such a manner that guarantees the high pulse width is a full

pulse. CPUCLK on latency is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.

Internal

CPUCLK

PCICLK (0:4)

CPU_STOP#

PCI_STOP# (HIGH)

PD# (HIGH)

CPUCLK (0:2)

Notes:

1. All timing is referenced to the internal CPUCLK.

2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized to the CPUCLKs inside PI6C106.

3. All other clocks continue to run undisturbed including SDRAMR.

4. PD# and PCI_STOP# are shown in a high (true) state.

PCI_STOP# Timing Diagram

PCI_STOP# is an asynchronous input to the PI6C106. It is used to turn off the PCICLK (0:5) clocks for low power operation. PCI_STOP#

is synchronized by the PI6C106 internally. PCICLK (0:5) clocks are stopped in a low state and started with a full high pulse width guaranteed.

PCICLK (0:5) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.

Internal

CPUCLK

Internal

PCICLK

PCICLK

(free-runningl)

CPU_STOP#

PCI_STOP#

PWR_DWN#

PCICLK

(external)

Notes:

1. All timing is referenced to the Internal CPUCLK (defined as inside the PI6C106 device.)

2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized

inside the PI6C106.

3. All other clocks continue to run undisturbed.

4. PD# and CPU_STOP# are shown in a high (true) state.

3

PS8546A 07/13/01

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