MC14568BD 데이터 시트보기 (PDF) - Motorola => Freescale
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MC14568BD Datasheet PDF : 12 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎACÎÎÎÎTERÎÎÎÎISTÎÎÎÎICSÎÎÎÎ(CLÎÎÎÎ= 50ÎÎÎÎpFÎÎÎÎ, TAÎÎÎÎ= 25ÎÎÎÎ_C)ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
Characteristic
Symbol
V
Min
Typ
Max
Unit
Output Rise Time
tTLH
5.0
—
180
360
ns
10
—
90
180
15
—
65
130
Output Fall Time
tTHL
5.0
—
100
200
ns
10
—
50
100
15
—
40
80
Minimum Pulse Width, C1, Q1/C2, or PCin Input
tWH
5.0
—
125
250
ns
10
—
60
120
15
—
45
90
Maximum Clock Rise and Fall Time,
C1, Q1/C2, or PCin Input
tTLH,
5.0
15
—
—
µs
tTHL
10
15
—
—
15
15
—
—
PHASE COMPARATOR
Input Resistance
Input Sensitivity, dc Coupled
Rin
5.0 to 15
—
106
—
MΩ
—
5.0 to 15
See Input Voltage
Turn–Off Delay Time,
PCout and LD Outputs
tPHL
5.0
—
550
1100
ns
10
—
195
390
15
—
120
240
Turn–On Delay Time.
PCout and LD Outputs
tPLH
5.0
—
675
1350
ns
10
—
300
600
15
—
190
380
DIVIDE–BY–4, 16, 64 OR 100 COUNTER (D1)
Maximum Clock Pulse Frequency
Division Ratio = 4, 64 or 100
fcl
MHz
5.0
3.0
6.0
—
10
8.0
16
—
15
10
22
—
Division Ratio = 16
5.0
1.0
2.5
—
10
3.0
6.3
—
15
50
9.7
—
Propagation Delay Time, Q1/C2 Output
Division Ratio = 4, 64 or 100
tPLH,
ns
tPHL
5.0
—
450
900
10
—
190
380
15
—
130
260
Division Ratio = 16
5.0
—
720
1440
10
—
300
600
15
—
200
400
PROGRAMMABLE DIVIDE–BY–N 4–BIT COUNTER (D2)
Maximum Clock Pulse Frequency
(Figure 3a)
fcl
5.0
1.2
1.8
—
MHz
10
3.0
8.5
—
15
4.0
12
—
Turn–On Delay Time, “0” Output
(Figure 3a)
tPLH
5.0
—
450
900
ns
10
—
190
380
15
—
130
260
Turn–Off Delay Time, “0” Output
(Figure 3a)
tPHL
5.0
—
225
450
ns
10
—
85
170
15
—
60
150
Minimum Preset Enable Pulse Width
tWH(PE)
5.0
—
75
250
ns
10
—
40
100
15
—
30
75
MOTOROLA CMOS LOGIC DATA
MC14568B
3
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