HS7541AKS 데이터 시트보기 (PDF) - Signal Processing Technologies

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HS7541AKS

12–Bit CMOS Multiplying DAC

Signal Processing Technologies 

GAIN TRIM

+15V

VREF (–10V)

2KΩ

D11 (MSB)

17

4 VREF

16

VDD RFB 18

INPUT

DATA

IO1 1

HS7541A

1KΩ

D0 (LSB) 15

GND

3

IO2 2

–

+

10KΩ

10KΩ

–

+

VOUT

390Ω

10KΩ

500Ω

Figure 5. Bipolar Operation

minal, may be anywhere between 10kΩ (the

feedback resistor alone when all digital inputs

are LOW) and 7.5kΩ (the feedback resistor in

parallel with approximately 30kΩ of the R-2R

ladder network resistance when any single bit is

HIGH). Static accuracy and dynamic perfor-

mance will be affected by these variations.

UNIPOLAR OPERATION

Figure 4 shows the connections to implement

digital unipolar operation of the HS7541A. The

reference voltage applied to VREF (pin17) may be

positive or negative. The 2KΩ potentiometer

tied to VREF, and the 1KΩ resistor in the feed-

back loop are both optional; they are needed

only when gain error must be trimmed to less

than 0.3% FSR. They should track each other to

better than 0.1%. It is not necessary that they

track the resistors internal to the HS7541A.

As shown in the figure, the output current of the

HS7541A is typically connected to an external

op amp, with its non-inverting input tied to

ground. The amplifier should be selected for

low input bias current and low drift over tem-

perature. To maintain the specified linearity, the

amplifier’s input offset voltage should be mulled

to less than ±200µV (0.1 LSB).

BIPOLAR OPERATION

Figure 5 shows the connections for bipolar

operation of the HS7541A. The digital input

coding is offset binary as shown in Table 2. As

is the case for unipolar operation, the gain trim

resistors can be omitted if minimum gain error

is not required. The op amp selection criteria

and offset nulling are the same as for unipolar

operation.

DIGITAL INPUT

1111 1111 1111

1000 0000 0000

0111 1111 1111

0000 0000 0000

I0UT

-0.99975 x VREF

-0.50000 x VREF

-0.49975 x VREF

0V

Table 1. Unipolar Input Coding

DIGITAL INPUT

1111 1111 1111

1000 0000 0001

1000 0000 0000

0100 0000 0000

0000 0000 0000

I0UT

-0.99951 x VREF

-0.00049 x VREF

0V

+0.50000 x VREF

+1.00000 x VREF

Table 2. Bipolar Input Coding

HS7541A

12-Bit CMOS Multiplying DAC

6

© Copyright 2000 Sipex Corporation

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