DAC312FR 데이터 시트보기 (PDF) - Analog Devices
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DAC312FR Datasheet PDF : 14 Pages
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DAC312
WAFER TEST LIMITS @ VS = ؎15 V, IREF = 1.0 mA, TA = 25؇C, unless otherwise noted. Output characteristics refer to both IOUT and IOUT.
Parameter
Symbol
Conditions
DAC312N
Limit
DAC312G
Limit
Units
Resolution
12
12
Bits min
Monotonicity
12
12
Bits min
Nonlinearity
± 0.05
± 0.05
%FS max
Output Voltage
Compliance
Voc
Full-Scale Current
Change <1/2 LSB
+10
+10
V max
–5
–5
V min
Full-Scale
Current
Full-Scale Symmetry
Zero-Scale Current
Differential
Nonlinearity
IFSS
IZS
DNL
VREF = 10.000 V
R14, R15 = 10.000 kΩ
Deviation from
Ideal Step Size
4.031
3.967
±1
0.1
± 0.012
± 1/2
4.063
3.935
±2
0.1
± 0.025
±1
mA max
mA min
µA max
µA max
%FS max
Bits (LSB) max
Logic Input Levels “0”
VIL
Logic Input Levels “1”
VIH
Logic Input Swing
VIS
VLC = GND
VLC = GND
0.8
0.8
V max
2
2
V min
+18
+18
V max
–5
–5
V min
Reference Bias
Current
I15
–2
–2
µA max
Power Supply
Sensitivity
PSSIFS+
PSSIFS–
V+ = +13.5 V to +16.5 V, V– = –15 V
V– = –13.5 V to –16.5 V, V+ = +15 V
± 0.001
± 0.001
± 0.001
± 0.001
%/%max
Power Supply
I+
Current
I–
VS = +15 V
IREF ≤ 1.0 mA
7
7
–18
–18
mA max
Power
VS = +15 V
Dissipation
PD
IREF ≤ 1.0 mA
375
375
mW max
NOTE
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
DICE CHARACTERISTICS
1. B1 (MSB)
2. B2
3. B3
4. B4
5. B5
6. B6
7. B7
8. B8
9. B9
10. B10
DIE SIZE 0.141 × 0.096 inch, 13,536 sq. mils (3.58 × 2.44 mm, 8.74 sq. mm)
11. B11
12. B12 (LSB)
13. VLC/AGND
14. VREF(+)
15. VREF(–)
16. COMP
17. V–
18. IO
19. IO
20. V+
–4–
REV. C
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