LND-TRN902 데이터 시트보기 (PDF) - Linear Dimensions Semiconductor

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LND-TRN902

PLL-FREQUENCY SYNTHESIZER

Linear Dimensions Semiconductor 

Theory of

Operation

The phase

detector and

charge pump

Programming

Standby

PLL-FREQUENCY SYNTHESIZER PROPOSED DATA SHEET

The TH7010 is a PLL frequency synthesizer

intended for use in a frequency generation loop

with a dual modulus prescaler and a VCO. The

VCO frequency is divided by the external dual

modulus prescaler. This divided signal is fed to

the internal A and N counters. The reference

frequency is fed to an internal R counter to define

the channel spacing. Both frequencies are

compared in the phase detector which drives the

charge pump. A lock detect is provided to monitor

the lock state of the loop. All blocks are program-

med by a 3 wire interface.

The division ratio can be calculated as follows :

FVCO = ( N x P + A) / R x FREF

FVCO : Output frequency of the external VCO

FREF : Reference oscillator frequency

N : divide ratio of the N counter 3 ≤ N ≤ 16380

A : divide ratio of the A counter 0 ≤ A ≤127

R : divide ratio of the R counter 3 ≤ R ≤ 65535

P : divide ratio of the external dual modulus

prescaler

The phase detector is a digital edge sensitive

comparator with UP and DOWN outputs. Both

outputs can be monitored at the outputs PO1 and

PO2. The phase detector drives a charge pump

which is a switch with a tristate state. The output

current can be programmed in 8 steps between

0.125 mA and 2 mA with a reference current of

100 µA.

If VFI < RFI, the charge pump delivers a positive

current to the external loop filter.

If VFI > RFI, the charge pump sinks a negative

current from the external loop filter.

The charge pump output can be inverted by

software.

Anti-backlash pulses are generated to extend the

very short phase difference between VFI and RFI.

The TH7010 can be programmed through a 3 wire

interface. Four different words can be sent over

this interface to program the internal registers. All

four words have a 2 bit address part and a

variable data part. When EN = L the data is

transferred. It is loaded into the internal registers

at the rising edge of EN. The last two bits which

are transferred form the address bits. When

EN = H, the input signals CLK and DATA are

internally disabled.

The Status Register contains all status informa-

tion.

The Reduced Status Register is a reduced

version of the Status Register.

The N and A Counter Register and the R Counter

Register contain the applicable counter values.

The programming of the device must start with

the loading of the Status Register.

The N, A and R counters can be loaded synchro-

nously or asynchronously. If synchronous loading

is selected, all counters are loaded when they

reach the value zero. As a result, the phase

difference between the divided VFI and RFI

signals remains the same.

For synchronous loading the following order of

programming must be followed :

1. programming of synchronous loading using the

Status Register

2. programming of the R counter

3. programming of the N/A counter. The rising

edge of EN enables the synchronous loading of

all counters at their zero value.

The TH7010 has two standby modes.

In standby mode 1, the whole device is powered down with the exception of the serial interface.

In standby mode 2, the serial interface and the input amplifiers are active. All other parts are powered

down.

Linear Dimensions, Inc. 445 East Ohio Street, Chicago, IL 60611 p 312.3211810 f 312.321.1830

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