LB1875 데이터 시트보기 (PDF) - SANYO -> Panasonic
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LB1875 Datasheet PDF : 17 Pages
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LB1875
Description of the LB1875
1. Speed control circuit
This IC uses the PLL speed control technique which allows stable, high-precision motor rotation with low jitter. The PLL circuit
performs phase comparison of the falling edge of the clock input (CLKIN) with the edge of the FG input. Control is based on the
differential output.
When the FGSEL pin is Low, only the falling edge of the FG signal is valid. When the pin is High or open, both edges are valid. When
both edges are used, the FG waveform precision becomes critical.
When using an external clock input (supplied from CLKIN pin), the FG servo frequency is determined by the following equation.
f (servo) = f (FG = Low)
FG
CLK
SEL
f (servo) = f /2 (FG = High or open)
FG
CLK
SEL
When using the internal clock, the FG servo frequency is determined by the following equation. The number of FG pulses and the
quartz oscillator frequency determine the motor rotation speed.
fFG (servo) = fOSC/N (FGSEL = Low)
fFG (servo) = fOSC/2N (FGSEL = High or open)
fOSC: Quartz oscillator frequency
N: Clock divisor (see table)
2. Output drive
This IC allows selection of PAM drive or direct PWM drive.
When the LIM pin is Low, the direct PWM mode is selected. The ON duty cycle of the UH, VH, and WH output (external bottom-
side transistor drive output) changes, thereby controlling the motor speed. Current control is also realized by changing the ON duty
cycle to limit the current. At this time, the Schmitt comparator output of the FG is supplied at the PWM pin. When bipolar
OUT
transistors are used externally, the top-side transistors should not have an integrated diode, but Schottky barrier diodes should be used
instead (to prevent feedthrough current caused by diode reverse recovery during PWM switching).
When the LIM pin is High or open, the PAM drive mode is selected. The PWMOUT pin carries the PWM signal. This output can drive
an external switching regulator circuit for varying the motor supply voltage and thereby controlling motor speed. Current control is
also realized by changing the motor supply voltage. In this case, a delay in the switching regulator circuit will cause a delay in the
current control action. During the delay, a higher current than the set current may flow, which must be taken into consideration when
selecting output transistors. For applications where the motor has variable speed and control at low motor voltages is required, the
lowest operation voltage is limited by the base voltage of the interface transistor for top-side output transistor drive. If this causes a
problem, the base voltage must be made low (for example by dividing the VREG voltage with resistors). When FETs are used as top-
side output transistors, types which can be used at low gate voltages must be selected.
3. Current limiting circuit
The current limiting circuit limits the peak current to the value I = V /Rf (V = 0.5V typ., Rf: current detector resistor). As
RF
RF
mentioned above, in PAM drive mode, a current higher than the set current may flow during the delay interval. If the capacitor
charge current of the switching regulator circuit is a problem, a smoothing capacitor may be inserted, with the negative side connected
to the RF pin.
If PWM noise is a problem in the RF waveform, a filter should be provided at the input.
No. 6002-9/17
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