SP9501KS 데이터 시트보기 (PDF) - Signal Processing Technologies
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SP9501KS Datasheet PDF : 9 Pages
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SPECIFICATIONS (continued)
(Typical
at
25˚C;
T
MIN
≤
T
A
≤
T;
MAX
V
DD
=
+5V,
V
SS
=
–5V,
V
REF
=
+3V;
CMOS
logic
level
digital
inputs;
specifications
apply
to
all
grades
unless
otherwise
noted.)
PARAMETER
MIN. TYP. MAX.
UNITS
CONDITIONS
POWER REQUIREMENTS
VDD
–J, –K
–A, –B
VSS
–J, –K
–A, –B
Power Dissipation
Note 5
+5V, ±3%; Note 4, 5
1.6
2.3
mA
1.6
2.9
mA
-5V, ±3%; Note 4, 5
1.6
2.3
mA
1.6
2.9
mA
16
mW
SWITCHING
CHARACTERISTICS
CS Setup Time
(tCSS)
25
ns
SCLK Fall to CS Fall
Hold Time
(tCSH0)
20
ns
SCLK Fall to CS Rise
Hold Time
(tCSH1)
0
ns
SCLK High Width
(tCH)
40
ns
SCLK Low Width
(tCL)
40
ns
DIN Setup Time
(tDS)
50
ns
DIN Hold Time
(tDH)
0
ns
CS High Pulse Width
(tCSW)
30
ns
ENVIRONMENTAL AND
MECHANICAL
Operating Temperature
–J, –K
0
–A, –B
–40
Storage
–60
Package
–_N
–_S
+70
°C
+85
°C
+150
°C
8-pin Plastic DIP
8-pin 0.15" SOIC
Notes:
1. Integral Linearity, for the SP9501, is measured as the arithmetic mean value of the magnitudes of the
greatest positive deviation and the greatest negative deviation from the theoretical value for any given
input condition.
2. Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two
adjacent digital input codes.
3. 1 LSB = 2*VREF/4,096.
4. VREF = 0V.
5. The following power up sequence is recommended: VSS (-5V), Vdd (+5V), VREF.
SP9501DS/02
SP9501 12-Bit, Low-Power Voltage Output
3
© Copyright 2000 Sipex Corporation
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