SP9600KN 데이터 시트보기 (PDF) - Signal Processing Technologies

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SP9600KN

12–Bit, Low Power Voltage Output D/A Converter

Signal Processing Technologies 

SPECIFICATIONS (continued)

(Typical

at

25˚C;

T

MIN

≤

T

A

≤

T;

MAX

V

DD

=

+5V,

DGND

=

0V,

V

REF

=

+3.5V;

AGND

=

+1.5V;

CMOS

logic

level

digital

inputs;

specifications

apply

to

all

grades

unless

otherwise

noted.)

PARAMETER

MIN. TYP. MAX.

UNITS

CONDITIONS

POWER REQUIREMENTS

VDD

-J, -K

-A, -B

Power Dissipation

0.1

0.18

0.1

0.25

0.5

Note 5

+5V, ±3%; Note 4, 5

mA

mA

mW

SWITCHING

CHARACTERISTICS

CS Setup Time

(tCSS)

25

ns

SCLK Fall to CS

Fall Hold Time

(tCSH0)

20

ns

SCLK Fall to CS Rise

Hold Time

(tCSH1)

0

ns

SCLK High Width

(tCH)

40

ns

SCLK Low Width

(tCL)

40

ns

DIN Setup Time

(tDS)

50

ns

DIN Hold Time

(tDH)

0

ns

CS High Pulse Width

(tCSW)

30

ns

ENVIRONMENTAL AND

MECHANICAL

Operating Temperature

-J, -K

0

+70

°C

-A, -B

-40

+85

°C

Storage

-60

+150

°C

Package

–_N

8-pin Plastic DIP

–_S

8-pin 0.15" SOIC

Notes:

1.

2.

3.

4.

Integral Linearity, for the SP9600, is measured as the arithmetic mean value of the magnitudes of

the greatest positive deviation and the greatest negative deviation from the theoretical value for any

given input condition.

Differential Linearity is the deviation of an output step from the theoretical value of 1 LSB for any two

adjacent digital input codes.

1 LSB = (VREF - AGND)/4,096.

VREF , AGND = 2.5V.

5.

The following power up sequence is recommended: VDD (+5V), VREF

SP9600DS/04

SP9600 12-Bit, Low Power Voltage Output D/A Converter

3

© Copyright 2000 Sipex Corporation

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