WM8148 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8148 Datasheet PDF : 43 Pages
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WM8148
PIN CONFIGURATION
DVDD1
RLC
AVDD4
DGND3
MCLK
AGND5
VSMP
DGND1
OP0
OP1
OP2
OP3
48 47 46 45 44 43 42 41 40 39 38 37
1
36
2
35
3
34
4
33
5
32
6
31
7
30
8
29
9
28
10
27
11
26
12
25
13 14 15 16 17 18 19 20 21 22 23 24
RINP
AGND1
OVRD
VRLC
VRX
VRT
AGND3
VRB
AVDD2
AVDD3
DGND4
AGND4
Production Data
ORDERING INFORMATION
DEVICE
XWM8148CFT/V
TEMP. RANGE
0 to 70oC
PACKAGE
48-pin 1mm
thick body TQFP
PIN DESCRIPTION
PIN NAME
1
DVDD1
2
RLC
TYPE
Supply
Digital input
3
AVDD4
4
DGND3
5
MCLK
Supply
Ground
Digital input
6
AGND5
7
VSMP
Ground
Digital IO
8
DGND1
9
OP0
10
OP1
11
OP2
12
OP3
13 DVDD2
14
OP4
15
OP5
16
OP6
17
OP7
18
OP8
19
OP9
20
OP10
21
OP11
Ground
Digital output
Digital output
Digital output
Digital output
Supply
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
DESCRIPTION
Digital supply (3.3V to 5V) for digital inputs and SDO.
Selects whether reset level clamp is applied, active high. If RLC is required on every
pixel then this pin can be tied high.
Analogue supply (5V).
Digital ground (0V).
Master clock. This clock is applied at N times the input pixel rate (N = 12, 8, 6, or
4 dependent on input sampling mode). MCLK is divided internally by N to generate
internal clocks and to provide the clock source for digital logic.
Analogue ground (0V).
Video sample synchronisation pulse. This pin may be either an input (default) or output.
Input: This signal is pulsed externally
to synchronise the WM8148’s video
input sample instant and the N-phase
internal clock to CCD clocks and
interface bus timing.
Output: This signal is pulsed internally to
flag the video input sample instant, to allow
the CCD clocks and interface bus to be
synchronised to the WM8148.
Digital ground (0V) for output drivers.
12-bit signal data output bus. Data is output MSB on OP[11] and LSB on pin OP[0].
See description of pins 14-21 for mode definitions.
Digital supply (3.3V-5V) for Digital IO pins and OP0 to OP3
12-bit bi-directional data bus. On pins OP[4] to OP[11], signal data is output if OEB = 0
and register write data is input if OEB = 1.
There are five main modes:
• Hi-Z: when OEB = 1
• Output 12-bit: twelve bit signal data output from bus
• Output 8-bit muxed: signal data output on OP[11:4] at 2 ∗ ADC conversion rate
• Input 8-bit: register write data input on OP[11:4]
• Output 8-bit: register readback data output on OP[11:4]
WOLFSON MICROELECTRONICS LTD
PD Rev 4.0 April 1999
2
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