WM8148 데이터 시트보기 (PDF) - Wolfson Microelectronics plc

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WM8148

12-bit/12MSPS CCD/CIS Analogue Front End/Digitiser

Wolfson Microelectronics plc 

WM8148

RESET LEVEL CLAMP

MCLK

Production Data

VSMP

RLC = 0

RLC = 1

tRLCSU

tRLCH

Figure 3 Reset Level Clamp Control Timing

tPER

MCLK

MODE 8-13

CL SMALL = 0

MODE 8-13

CL SMALL = 1

MODE 0-5

CL SMALL = 0

MODE 0-5

CL SMALL = 1

OFF

tRLCPD

OFF

tRLCPD

OFF

OFF

tRLCPD

ON

tRLCPD

ON

tRLCPD

tRLCPD

ON

tRLCPD

tRLCPD

ON

OFF

OFF

OFF

OFF

Figure 4 Internal Clamp Signal (CL) Timing

TEST CONDITIONS

AVDD = 4.75 to 5.25V, DVDD1 and DVDD2 = 2.97 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 48MHz unless

otherwise stated (AVDD denotes the voltage applied to all AVDD pins).

PARAMETER

SYMBOL TEST CONDITIONS

MIN

TYP

MAX

UNITS

MCLK period

Propagation delay

tPER

tRLCPD

20.8

ns

15

ns

Set-up time

tRLCSU

10

ns

Hold time

tRLCH

10

ns

Notes: 1. Internal clamp signal (CL) timing may be relative to either the falling or rising edge of MCLK depending on the setting of

control bits RESREF[3:0].

2. Parameters are measured at 50% of the rising/falling edge.

WOLFSON MICROELECTRONICS LTD

PD Rev 4.0 April 1999

9

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