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SI9961 데이터 시트보기 (PDF) - Vishay Semiconductors

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상세내역
제조사
SI9961
Vishay
Vishay Semiconductors Vishay
SI9961 Datasheet PDF : 8 Pages
1 2 3 4 5 6 7 8
Si9961
Vishay Siliconix
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to Common Pin
V+ Supply Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to 16 V
Pin (FAULT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VCC + 0.3 V
Pin (Output A & B, Source A & B) . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V
Pin (All Others) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to V+ + 0.3 V
Maximum Clamp Current
Output A, Output B (Pulsed 10 ms at 10% duty cycle) . . . . . . . . . . . . "1.8 A
Pin (All Others) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . "20 mA
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 to 150_C
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C
Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C
Power Dissipation (Package)a
24-Pin SOICb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.125 W
Thermal Impedance (QJA)a
24-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40_C/W
Notes
a. Device mounted with all leads soldered or welded to PC board.
b. Derate 25 mW/_C above 25_C.
SPECIFICATIONS
Parameter
Symbol
Bridge Outputs (A4, A5)
High Level Output Voltage
VOH
Low Level Output Voltage
VOL
Clamp Diode Voltage
VCL
Amplifier Gain
Dynamic Crossover Current
Slew Rate
SR
Small Signal Bandwidth (3 dB)
Input Deadband
A2, Loop Compensation Amplifier
Input Offset Voltage
Input Bias Current
Unity Gain Bandwidth
Slew Rate
Power Supply Rejection Ratio
Open Loop Voltage Gain
Output Voltage Swing
VOS
IB
SR
PSRR
AVOL
VO
A3, Current Sense Amplifier
Input Offset Voltage
Input Impedance
Small Signal Bandwidth (3 dB)
Common Mode Rejection Ratio
Slew Rate
Gain
Input Common-Mode Voltage Range
Output Voltage Swing
Supply
VOS
RIN
CMRR
SR
VCM
VO
ICC
Supply Current (Normal)
IV+
IDD
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2
Test Conditions
Unless Otherwise Specified
V+ = 12 V "10%, VDD = 11.6 V "10%
VCC = 5 V "10%, VREF= GND = 0 V
VREF = 5 V "5%
IOH = 1.0 A, VDD = 10.2 V, OA2= VREF "1 V
IOL = 1.0 A, OA2 = VREF "1 V
IF = 1.0 A, ENABLE = High
Output VRANGE = VREF "2 V
Measured at VDD
Limits
C Suffix 0 to 70_C
Minb Typa Maxb Unit
8.0
9.1
0.6
1.1
V
2.5
12
16
18
V/V
10
mA
1
V/mS
0.2
MHz
60
60
mV
Gain Select = High, IA2= 5 V
RLOAD = 10 kW, CLOAD = 100 pF to VREF
@ 10 kHz
RLOAD = 10 kW to VREF
8
8
mV
50
1
1
50
80
50
nA
MHz
V/ms
dB
VREF 2
VREF +2 V
ISENSEIN+ to ISENSEIN
RLOAD = 10 kW, CLOAD = 100 pF to VREF
@ 5 kHz
To GND
RLOAD = 10 kW, CLOAD = 100 pF to VREF
Static, No Load
RETRACT = High
ENABLE = Low
5
5
mV
5
kW
1
MHz
50
dB
2
V/ms
3.9
4
4.1
V/V
0.3
VREF 2
2
V
VREF +2
0.01
2
5
mA
5
13
Document Number: 70014
S-20883Rev. G, 24-Jun-02

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