FX375 데이터 시트보기 (PDF) - CML Microsystems Plc

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FX375

Private Squelch Circuit

CML Microsystems Plc 

Timing Information ...... Control instructions are input to the FX375 by serial (figure 3) or parallel

(figure 4) means, using Data Inputs and Load/Latch as shown in the diagrams below.

D4

SERIAL MODE

ENABLE

D5

SERIAL CLOCK

SERIAL DATA

INPUT

t SMS

t DS

tPWH

t PWL

t DH

LOAD/LATCH

Fig.3 Serial Load Timing

t LL

tLLW

Min.

Typ.

Max. Unit

Serial

Figure 3

Serial Mode Enable Set Up Time – (t )

SMS

Clock 'High' Pulse Width – (tpWH)

Clock 'Low' Pulse Width – (t )

pWL

Data Set Up Time – (tDS)

Data Hold Time – (t )

DH

Load/Latch Set Up Time – (t )

LL

Load/Latch Pulse Width – (t )

LLW

250

–

250

–

250

–

150

–

50

–

250

–

150

–

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

–

ns

Parallel

Figure 4

Data Valid Time – (t )

VP

Load Time – (tL)

Fall Time – (t )

F

Data Hold Time – (t )

H

200

–

150

–

–

–

50

–

–

ns

–

ns

50

ns

–

ns

Serial Loading Sequence : With Load/Latch at logic '0' serial data is loaded in the sequence :-

D5, D4, D3, D2, D1, D0, Rx/Tx, Private Enable. When these 8 bits have been clocked in on the rising clock edge,

data is latched by strobing the Load/Latch input – " 0 – 1 – 0 " (Figure 3).

Table 4 Timing

- DATA INPUTS -

t VP

D0 – D5

Rx/Tx

PRIVATE ENABLE

LOAD/LATCH

tL

tF

tH

Fig.4 Parallel Load Timing

LOAD DATA

6

DATA LATCHED

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