EPM3256AQC208-10 데이터 시트보기 (PDF) - Altera Corporation

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EPM3256AQC208-10

Programmable Logic Device Family

Altera Corporation 

®

June 2006, ver. 3.5

MAX 3000A

Programmable Logic

Device Family

Data Sheet

Features...

■ High–performance, low–cost CMOS EEPROM–based programmable

logic devices (PLDs) built on a MAX® architecture (see Table 1)

■ 3.3-V in-system programmability (ISP) through the built–in

IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with

advanced pin-locking capability

– ISP circuitry compliant with IEEE Std. 1532

■ Built–in boundary-scan test (BST) circuitry compliant with

IEEE Std. 1149.1-1990

■ Enhanced ISP features:

– Enhanced ISP algorithm for faster programming

– ISP_Done bit to ensure complete programming

– Pull-up resistor on I/O pins during in–system programming

■ High–density PLDs ranging from 600 to 10,000 usable gates

■ 4.5–ns pin–to–pin logic delays with counter frequencies of up to

227.3 MHz

■ MultiVoltTM I/O interface enabling the device core to run at 3.3 V,

while I/O pins are compatible with 5.0–V, 3.3–V, and 2.5–V logic

levels

■ Pin counts ranging from 44 to 256 in a variety of thin quad flat pack

(TQFP), plastic quad flat pack (PQFP), plastic J–lead chip carrier

(PLCC), and FineLine BGATM packages

■ Hot–socketing support

■ Programmable interconnect array (PIA) continuous routing structure

for fast, predictable performance

■ Industrial temperature range

Table 1. MAX 3000A Device Features

Feature

Usable gates

Macrocells

Logic array blocks

Maximum user I/O

pins

tPD (ns)

tSU (ns)

tCO1 (ns)

fCNT (MHz)

EPM3032A

600

32

2

34

4.5

2.9

3.0

227.3

EPM3064A

1,250

64

4

66

4.5

2.8

3.1

222.2

Altera Corporation

DS-MAX3000A-3.5

EPM3128A

2,500

128

8

98

5.0

3.3

3.4

192.3

EPM3256A

5,000

256

16

161

7.5

5.2

4.8

126.6

EPM3512A

10,000

512

32

208

7.5

5.6

4.7

116.3

1

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