EPM7256EGC192-15 데이터 시트보기 (PDF) - Altera Corporation

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EPM7256EGC192-15

Programmable Logic Device Family

Altera Corporation 

MAX 7000 Programmable Logic Device Family Data Sheet

The MAX 7000 architecture includes four dedicated inputs that can

be used as general-purpose inputs or as high-speed, global control

signals (clock, clear, and two output enable signals) for each

macrocell and I/O pin. Figure 1 shows the architecture of EPM7032,

EPM7064, and EPM7096 devices.

Figure 1. EPM7032, EPM7064 & EPM7096 Device Block Diagram

INPUT/GLCK1

INPUT/GCLRn

INPUT/OE1

INPUT/OE2

8 to 16

I/O pins

LAB A

8 to 16

I/O

Control

Block

Macrocells

1 to 16

36

16

LAB B

36

Macrocells

17 to 32

16

8 to 16

I/O

Control

Block

8 to 16

I/O pins

8 to 16

LAB C

8 to 16

I/O

Control

Block

Macrocells

33 to 48

PIA

36

16

8 to 16

LAB D

36

Macrocells

49 to 64

16

8 to 16

I/O

Control

Block

8 to 16

8 to 16

8 to 16

I/O pins

8 to 16

I/O pins

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