STLVD111 데이터 시트보기 (PDF) - STMicroelectronics
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STLVD111 Datasheet PDF : 12 Pages
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STLVD111
Electrical characteristics
Table 7.
Symbol
Driver electrical characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise
specified Note: 1, 2)
Parameter
Test condition
Min. Typ. Max. Unit
VBB
ICCD
CIN
COUT
VIH
VIL
II
Output reference voltage
Power supply current
Input capacitance
Output capacitance
Logic input high threshold
Logic input low threshold
Logic input current
VCC = 2.5 V
All driver enabled and loaded
VI = 0V to VCC
1.15
VCC = 2.5 V
2
VCC = 2.5 V
VCC = 2.5 V, VIN = VCC or GND
1.25 1.35 V
125 160 mA
5
pF
5
pF
V
0.8
V
±10 µA
Note: 1 All currents into device pins are positive; all currents out of device pins are negative. All
voltages are referenced to device ground unless otherwise specified
2 All typical values are given for VCC = 2.5V and TA = 25°C unless otherwise stated
Table 8. LVDS timing characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless otherwise
specified)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
tTLH, tTHL Transition time
RL = 100 Ω, CL = 5 pF,
Figure 7., Figure 8.)
220 300
ps
tPHL, tPLH
fMAX
Propagation delay time
Maximum input frequency
Bank skew
(Figure 7., Figure 8.)
(Figure 3.)
2
2.5
ns
700
900
MHz
50
tSKEW
Part to part skew
Pulse skew
(Figure 4.)
(Figure 5.)
100
ps
50
Table 9. Control register timing characteristics (TA = -40 to 85 °C, VCC = 2.5V ± 5%, unless
otherwise specified)
Symbol
Parameter
Test condition
Min. Typ. Max. Unit
fMAX
ts
th
trem
tW
Maximum frequency of shift register (Figure 9.)
Clock to SI setup time
(Figure 9.)
Clock to SI hold time
(Figure 9.)
Enable to clock removal time
(Figure 9.)
Minimum clock pulse width
(Figure 9.)
100
150
MHz
2
ns
1.5
ns
1.5
ns
3
ns
7/19
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