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PSD301 데이터 시트보기 (PDF) - Waferscale Integration

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PSD301
Waferscale
Waferscale Integration Waferscale
PSD301 Datasheet PDF : 88 Pages
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10.0
I/O Port
Functions
PSD3XX Family
The PSD3XX has three I/O ports (Ports A, B, and C) that are configurable at the bit level.
This permits great flexibility and a high degree of customization for specific applications.
The next section describes the control registers for the ports. Following that are sections
that describe each port. Figures 5 through 7 show the structure of Ports A through C,
respectively.
Note: any unused input should be connected directly to ground or pulled up to VCC
(using a 10Kto 100Kresistor).
10.1 CSIOPORT Registers
Control of the ports is primarily handled through the CSIOPORT registers. There are 24
bytes in the address space, starting at the base address labeled CSIOPORT. Since the
PSD3XX uses internal address lines A15-A8 for decoding, the CSIOPORT space will
occupy 2 Kbytes of memory, on a 2 Kbyte boundary. This resolution can be improved to
reduce wasted address space by connecting lower order address lines (A7 and below)
to Port C. Using this method, resolution down to 256 Kbytes may be achieved. The
CSIOPORT space must be defined in your PSDsoft design file. The following tables list
the registers located in the CSIOPORT space.
16-Bit Users Note
When referring to Table 5B, realize that Ports A and B are still accessible on a byte basis.
Note: When accessing Port B on a 16-bit data bus, BHE must be low.
Table 5A. CSIOPORT Registers for 8-Bit Data Busses
Register Name
Offset (in hex)
from CSIOPORT
Base Address
Port A Pin Register
+2
Port A Direction Register
+4
Port A Data Register
+6
Port B Pin Register
+3
Port B Direction Register
+5
Port B Data Register
+7
Power Management Register (Note 1)
+10
Page Register
+18
NOTE: 1. ZPSD only.
Table 5B. CSIOPORT Registers for 16-Bit Data Busses
Register Name
Offset (in hex)
from CSIOPORT
Base Address
Port A/B Pin Register
+2
Port A/B Direction Register
+4
Port A/B Data Register
+6
Power Management Register (Note 1)
+10
Page Register
+18
NOTE: 1. ZPSD only.
Type of
Access
Allowed
Read
Read/Write
Read/Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
Type of
Access
Allowed
Read
Read/Write
Read/Write
Read/Write
Read/Write
15

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