PSD301 데이터 시트보기 (PDF) - Waferscale Integration

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PSD301

Low Cost Microcontroller Peripherals

Waferscale Integration 

Figure 1.

PSD3XX

Family

Architecture

PSD3XX Family

AD8–AD15

A11–A15

L A8–A10

A

T

A19/CSI

C

H

ALE/AS

RD

WR

RESET

ALE/AS

OPTIONAL

PAGE LOGIC*

P3–P0

PAD A

13 P.T.

CSIOPORT

A19/CSI

ALE/AS

RD

WR

RESET

A16–A18

LOGIC IN

PROG.

PORT

EXP.

PAD B

27 P.T.

CS8–

CS10

PORT

C

PC0–

PC2

AD0–AD7

L

A

T

C

H

D8–D15

ES7

ES6

ES5

ES4

ES3

ES2

ES1

ES0

16/8

MUX

EPROM

256Kb TO 1Mb

D8–D15

CS0–

CS7

PROG.

PORT

EXP.

PORT

B

PB0–

PB7

D0–D7

CSIOPORT

ALE/AS

RD/E/DS

WR/R/W

BHE/PSEN

RESET

A19/CSI

OPTIONAL

RS0

SRAM

16K BIT

**

A0–A7

AD0–AD7/D0–D7

TRACK MODE

SELECTS

PROG.

PORT

EXP.

PORT

A

PA0–

PA7

PROG.

CONTROL

SIGNALS

PROG. CHIP

CONFIGURATION

X8, X16

MUX or NON–MUX BUSSES

SECURITY MODE

**Not available for 3X1 devices.

**SRAM not available on “R” versions.

3

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