AD9561JR 데이터 시트보기 (PDF) - Analog Devices

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AD9561JR

Pulse Width Modulator

Analog Devices 

ANALOG DEVICES FAX-ON-DEMAND HOTLINE - Page

AD9561

CLOCK

DATA

CONTROL

OUlPUT

Figure 1. Pulse Pattern Example

THEORY OF OPERATION

General

The AD9561 is a mixed signal IC designed to provide high-

///Ii///// ~ speed pulse width modulation in laser printers and copiers. It

uses high performance analog circuits to achieve high resolution

pulse control without requiring the excessively high clock rates

of an all digital solution.

OB J \\\\\\\\\~ Becauseof the sensitivity of analog circuitsto digital crosstalk,

PCB layout is criticalfor achievingoptimum results. Pleaseread the

layout section at the end of this data sheet and follow suggestions

S completelyfor bestperformance.

O The AD9561 was designed to facilitate either higher effective

1##1/ ~\\\\\~ resolution or photo-realistic image reproduction on low cost

L laser print platforms. Its 8-bit pulse width resolution and pulse

E positioning capabilities combine to offer the highest level of gray

shading and resolution enhancement flexibility available. It

TE also includes an autocalibration circuit to minimize external

LEADING EDGE

MODULATION

TRAJUNG EDGE

MODULATION

DUAL EDGE

MODULATION

Figure 2. Modulation Modes

Pulse positioning within the CLOCK period is defined by the

following table:

components, and eliminates an extra burden on the system

Table I. Truth Table

microprocessor.

The Functional Block Diagram illustrates the analog content,

SEM/DEM

LEMJTEM

Alignment

comprising ramp generators, DACs and comparators that

generate a series of pulses. These pulses are combined in the

output logic to form PWM OUT pulses whose width is propor-

tional to the 8-bit DATA and whose position is determined by

the SEMIDEM and LEMtrEM inputs.

The AD9561 employs a proprietary ramp topology that

1

1

LEM

1

0

TEM

0

X

DEM

Single-Edge Modulation offers two options in which one edge is

modulated while the other remains fixed relative to the CLOCK.

eliminates the loss of dynamic range at the ends of the ramp.

The Functional Block Diagram is shown for illustration purposes

only and does not represent the actual implementation.

Modulation Modes

For Leading-Edge Modulation, the rising edge of the pulse is

delayed from the leading edge of the CLOCK proportional to

DATA, and the falling edge remains fixed at the end of the

CLOCK period. This may also be called "right-hand justified."

Positioning the width controlled pulses at the beginning, middle

or end of the CLOCK period, as shown in Figure 2, adds

significantly to the flexibility of the AD9561. This is accom-

plished through control bit SEMIDEM and LEM/TEM. These

Similarly, Trailing-Edge Modulation has the rising edge fixed

on the beginning of the CLOCK period and the falling edge

delayed proportional to DATA. This can be called "left-hand

justified."

acronyms represent Single-Edge Modulation/Dual-Edge

Modulation and Leading-Edge Modulation/Trailing-Edge

Modulation. SEMIDEM and LEMtrEM are collectively

identified as CONTROL.

Dual-Edge Modulation is often called "center justified" because

the delay of both edges varies relative to the CLOCK. With

increasing values for DATA, pulse width increases with its

center remaining constant proportional to the CLOCK.

Like DATA, modulation control inputs SEM/DEM, and

LEM/TEM can be updated at the CLOCK rate up to60MHz.

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