ADM8696(Rev0) 데이터 시트보기 (PDF) - Analog Devices
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ADM8696 Datasheet PDF : 12 Pages
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ADM8696/ADM8697
Table I. ADM8696, ADM8697 Reset Pulse Width and Watchdog Timeout Selections
OSC SEL
OSC IN
Watchdog Timeout Period
Normal
Immediately After Reset
Reset Active Period
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLKS
400 ms × C/47 pF
100 ms
1.6 s
4096 CLKS
1.6 s × C/47 pF
1.6 s
1.6 s
512 CLKS
200 ms × C/47 pF
50 ms
50 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
WDI
WDO
t2
t3
RESET
t1
t1
t1
t1 = RESET TIME
t2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
Figure 3. Watchdog Timeout Period and Reset Active Time
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms, but these times to be adjusted as
shown in Table I. Figure 4 shows the various oscillator configu-
rations that can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. This gives the mi-
croprocessor time to reinitialize the system. If OSC IN is low,
the 100 ms watchdog period becomes effective after the first
transition of WDI. The software should be written such that the
I/O port driving WDI is left in its power-up reset state until the
initialization routines are completed and the microprocessor is
able to toggle WDI at the minimum watchdog timeout period of
70 ms.
COSC
8 OSC SEL
ADM869x
7 OSC IN
Figure 4b. External Capacitor
NC
8 OSC SEL
ADM869x
NC
7 OSC IN
Figure 4c. Internal Oscillator (1.6 s Watchdog)
NC
8 OSC SEL
ADM869x
7 OSC IN
Figure 4d. Internal Oscillator (100 ms Watchdog)
Watchdog Output (WDO)
The Watchdog Output WDO provides a status output that goes
low if the watchdog timer “times out” and remains low until set
high by the next transition on the watchdog input. WDO is also
set high when LLIN goes below the reset threshold.
CLOCK
0 TO 500kHz
8 OSC SEL
ADM869x
7 OSC IN
Figure 4a. External Clock Source
–6–
REV. 0
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