MC145750VFU 데이터 시트보기 (PDF) - Motorola => Freescale

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MC145750VFU

QPSK Encoder

Motorola => Freescale 

PIN DESCRIPTIONS

POWER SUPPLY

VSS

Digital Ground (Pins 6, 44)

These are the negative power supply input pins to the digi-

tal portion of the device and are connected to ground (0 V).

VDD

Positive Power Supply Input (Pins 7, 43)

These are the positive power supply input pins to the digi-

tal portion of the device. Typical operating voltage range is

3.3 V at DAref3 = H, 5.0 V at DAref1 = H. Power should be

fed simultaneously with DAVDD pin in order to avoid any pos-

sible damage to the device.

DAVDD

Positive Power Supply Input for DACs (Pin 13)

This is the positive power supply input pin to the analog

portion of the device. Typical operating voltage range is 2.7 V

to 5.5 V.

DAVSS

Analog Ground for DACs (Pin 14)

This is the negative power supply pin to the analog portion

of the device and is connected to ground.

MODE CONTROL AND TEST

MODE0 – MODE2

Normal/Test Mode Select (Pins 1, 2, 3)

These pins must be connected to ground for normal opera-

tion. For system test, PN pattern generation mode will be

performed when MODE0 = H and MODE1, MODE2 = L.

PN511 signal is fed to the encoder instead of input data from

TXD pin. Data shift timing is the same as the normal opera-

tion mode and burst timing indicated by DS pin is still valid for

the device. The PN511 signal is monitored at the PNO pin.

TEST

Test Mode (Pin 4)

The device operates normally while this pin is held low.

When this signal is high, the device enters into factory test

mode. Only one mode is allowed to be enacted by user for

PN Mode.

DRATE

Data–Rate Select (Pin 9)

This pin can select high data rate when it is low, such as in

PHS applications.

QPSK

(D)QPSK/π/4–Shift QPSK Mode Select (Pin 10)

The device operates as a π/4–QPSK Encoder when this

pin is held high. By making this pin low, it functions as non–

shift differential QPSK Encoder. All of the functions are the

same in both modes.

PN0/TB8

PN511 Test Pattern Output/Test Bus 8 (Pin 23)

This is the output data of PN511 test–pattern in normal

mode. When the PN pattern generator outputs to this pin, it

can be output I/Q pins and data from TXD pin may be ig-

nored. If the DS signal is L, I/Q pins stop but PN data stream

may be output.

TB0 – TB7

Test Bus (Pins 24, 26 – 32)

These pins are used in factory test and should be con-

nected to ground for normal operation.

PLL

Int/Ext PLL Clock Select (Pin 41)

When this pin is connected to ground, the PLL is active

and timing will be generated internally. When this pin is con-

nected to VDD, timing should be applied to the ECLK pin.

DIGITAL INTERFACE PINS

BW/TB9

Burst Window Output/Test Bus 9 (Pin 22)

This output indicates when modulated baseband I/Q sig-

nals are output from this device. This pin is used as the trans-

mission control signal for saving power for RF.

ECLK

External Clock Input (Pin 42)

When the internal timing generator with PLL is not used in

the system, this pin must have 15.36 MHz applied as a sys-

tem clock for this device. This pin is connected to ground for

normal operation.

DCLK

Data Shift Clock Input (Pin 45)

This is the shift clock input for the transmit data input and is

typically 384 kHz for the PHS (DRATE Pin = L) and 42 kHz

for the PDC (DRATE Pin = H) application. The data input oc-

curs at the rising edge of the DCLK. For burst–type systems

such as the TDMA data transmission applications, this signal

must be synchronized with the rising/falling edge of the DS

pin (Data Slot Timing Input).

DS/STBY

Data Slot Timing/Standby Input (Pin 46)

For burst–type, this input signal indicates when transmit

data are valid for the device. Its duration must be equal with

the number of input data to the device, and its transition must

be aligned with the rising edge of the DCLK signal.

When a logic L is applied to this pin, all digital portions ex-

cept the timing generator are not clocked and the device is in

a low power dissipation mode. When a logic H is applied con-

tinuously, all input data are encoded as valid data.

TXD

Transmit Data Input (Pin 47)

Data bit streams to be transmitted are input to this pin. The

data is valid only when the DS (Pin 46) is asserted (high). Its

transition should be synchronized with rising edge of the

DCLK (Pin 45).

MOTOROLA

MC145750

5

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