MC145750VFU 데이터 시트보기 (PDF) - Motorola => Freescale

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MC145750VFU

QPSK Encoder

Motorola => Freescale 

ERST/PDN

External Reset/Power Down Input (Pin 48)

When a logic L is applied to this pin, it forces a complete

power down. When at start up, VDD goes high, it is recom-

mended that a logic L, then a logic H be applied to this pin to

start up and reset all digital portions.

ANALOG INTERFACE PINS

Qout

Filtered Quadrature–Phase Output (Pin 15)

This is the modulated quadrature–phase signal output and

the amplitude is typically 550 mV p–p at VDD = 3 V in PN test

mode. The output dc resistance is approximately 50 Ω.

Iout

Filtered In–Phase Output (Pin 20)

This is the modulated in–phase signal output and ampli-

tude is typically 500 mV p–p at VDD = 3 V in PN test mode.

The output dc resistance is approximately 50 Ω.

DAC AND PLL SETTING

DAb

Reference Bias Setting Pin to DACs (Pin 12)

A resistor connected to ground from this pin determines

the reference current value for internal DACs. This resistor’s

value is 200 kΩ typically.

DAref

Ripple Filter Capacitor (Pin 16)

A capacitor connected to ground from this pin acts as a rip-

ple filter for the internal DACs’ reference voltage. This capac-

itor’s value is 0.1µF, typically.

DAref1 – DAref3

Reference Bias Setting to DACs (Pin 17 – 19)

These pins determine the reference voltage for internal

DACs in conjunction with DAb pin. At 3 V operation, DAref1

pin should be connected to VDD. DAref2 pin should be con-

nected to VDD at 3.3 V. DAref3 pin should be connected to

VDD at 5 V. The two other pins for the respective cases must

be left open.

PB1, PB2

PLL Bias (Pins 35, 38)

This pin determines the bias of the PLL. Its recommended

values are shown in Table 1 and it depends on operating volt-

age.

Cf

Loop Filter Capacitor (Pin 39)

Input from Cf pin is fed directly as the internal VCO control

signal.

PCO

Phase Comparator Output (Pin 40)

Connect an LPF as loop filter for the PLL. Refer to the ap-

plication figure for recommended values.

Pin

3 MODE0

10 QPSK

9 DRATE

17 DAref1

18 DAref2

19 DAref3

41 PLL

48 ERST/PDN

L

Normal Mode

Non–Shift

High Speed

—

—

—

PLL Operation

Mode

Power Down

Table 1. Function Table

H

Remarks

PN Pattern These settings are independent of power supply.

/4–Shift

Low Speed To be determined setting high or low speed data rate.

VDD = 5 V

VDD 3.3 V

VDD 3.0 V

Ext Clock Mode

These pins should be held high depending on power supply voltage and

others should be left open.

In case of external clock mode, TX data rate must be set to a frequency

of 1/40 when DRATE = L, and must be set to a frequency of 1/320

when DRATE = H. Max data rate is limited by power supply.

Normal Operation Digital circuits reset condition will be released by rising edge of this

input.

SERIAL DATA IN

MC145750

6

ROLL–OFF

FILTER

SERIAL TO

Xk

PARALLEL

CONVERSION

Yk

DIFFERENTIAL

ENCODING

Ik

Qk

ROLL–OFF

FILTER

Figure 2. DQPSK Baseband Signal Generation

TO DAC

TO DAC

MOTOROLA

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