UPC8105GR 데이터 시트보기 (PDF) - NEC => Renesas Technology
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UPC8105GR Datasheet PDF : 16 Pages
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µPC8105GR
PIN EXPLANATION
ASSIGN- SUPPLY PIN
PIN NO. MENT
VOL. (V) VOL.(V) FUNCTION AND APPLICATION
EQUIPMENT CIRCUIT
1
LOin
−
0
LO input for phase shifter.
This input impedance is 50 Ω
matched internally.
1
50 Ω
2
LOin
−
2.4 Bypass of LO input.
This pin is grounded through
2
internal capacitor.
Open in case of single ended.
3
GND
0
8
−
Connect to the ground with
minimum inductance.
Track length should be kept as
short as possible.
4
I
VCC/2
−
Input for I signal. This in put
impedance is larger than 20 kΩ.
Relations between amplitude and
VCC/2 bias of input signal are
following.
VCC/2 (v) Amp. (mVp-p) *1
≥ 1.35
400
4
5
≥ 1.5
600
≥ 1.75
1000
5
I
VCC/2
−
Input for I signal. This in put
impedance is larger than 20 kΩ.
VCC/2 biased DC signal should be
input.
6
Q
VCC/2
−
Input for Q signal. This in put
impedance is larger than 20 kΩ.
VCC/2 biased DC signal should be
input.
7
Q
VCC/2
−
Input for Q signal. This in put
impedance is larger than 20 kΩ.
Relations between amplitude and
7
6
VCC/2 bias of input signal are
following.
VCC/2 (v)
≥ 1.35
≥ 1.5
≥ 1.75
Amp. (mVp-p) *1
400
600
1000
12
MODout
−
1.5 Output from modulator.
This is emitter follower output.
12
*1: In case of that I/Q input signals are single ended.
Of course, I/Q signal inputs can be used either single endedly or differentially with proper terminations.
Data Sheet P10807EJ3V0DS00
5
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