DS21Q41BTN 데이터 시트보기 (PDF) - Dallas Semiconductor -> Maxim Integrated

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DS21Q41BTN

Quad T1 Framer

Dallas Semiconductor -> Maxim Integrated 

DS21Q41B

DS21Q41B PIN DESCRIPTION Table 1–4

Transmit Clock [TCLK]. 1.544 MHz primary clock.

Used to clock data through the transmit side formatter.

Transmit Serial Data [TSER]. Transmit NRZ serial

data. Sampled on the falling edge of TCLK when the

transmit side elastic store is disabled. Sampled on the

falling edge of TSYSCLK when the transmit side elastic

store is enabled.

Transmit Channel Clock [TCHCLK]. 192 KHz clock

which pulses high during the LSB of each channel. Syn-

chronous with TCLK when the transmit side elastic

store is disabled. Synchronous with TSYSCLK when

the transmit side elastic store is enabled. Useful for par-

allel to serial conversion of channel data, locating

robbed–bit signaling bits, and for blocking clocks in DDS

applications. See Section 12 for timing details.

Transmit Bipolar Data [TPOS and TNEG]. Updated

on rising edge of TCLK. Can be programmed to output

NRZ data on TPOS via the TCR1.7 control bit.

Transmit Channel Block [TCHBLK]. A user program-

mable output that can be forced high or low during any of

the 24 T1 channels. Synchronous with TCLK when the

transmit side elastic store is disabled. Synchronous

with TSYSCLK when the transmit side elastic store is

enabled. Useful for blocking clocks to a serial UART or

LAPD controller in applications where not all T1 chan-

nels are used such as Fractional T1, 384K bps service,

768K bps, or ISDN–PRI. Also useful for locating individ-

ual channels in drop–and–insert applications and for

per–channel loopback. See Section 12 for timing

details.

Transmit System Clock [TSYSCLK]. 1.544 MHz or

2.048 MHz clock. Only used when the transmit side

elastic store function is enabled. Should be tied low in

applications that do not use the transmit side elastic

store.

Transmit Link Clock [TLCLK]. 4 KHz or 2 KHz

(ZBTSI) demand clock for the TLINK input. See Section

12 for timing details.

Transmit Link Data [TLINK]. If enabled via TCR1.2,

this pin will be sampled during the F–bit time on the fal-

ling edge of TCLK for data insertion into either the FDL

stream (ESF) or the Fs bit position (D4) or the Z–bit posi-

tion (ZBTSI). See Section 12 for timing details.

Transmit Sync [TSYNC]. A pulse at this pin will estab-

lish either frame or multiframe boundaries for the

DS21Q41B. Via TCR2.2, the DS21Q41B can be pro-

grammed to output either a frame or multiframe pulse at

this pin. If this pin is set to output pulses at frame bound-

aries, it can also be set via TCR2.4 to output double–

wide pulses at signaling frames. See Section 12 for tim-

ing details.

Transmit Frame Sync [TFSYNC]. 8 KHz pulse. Only

used when the transmit side elastic store is enabled. A

pulse at this pin will establish frame boundaries for the

DS21Q41B. Should be tied low in applications that do

not use the transmit side elastic store. See Section 12

for timing details.

Receive Link Data [RLINK]. Updated with either FDL

data (ESF) or Fs bits (D4) or Z bits (ZBTSI) one RCLK

before the start of a frame. See Section 12 for timing

details.

Receive Link Clock [RLCLK]. 4 KHz or 2 KHz (ZBTSI)

demand clock for the RLINK input. See Section 12 for

timing details.

Receive Clock [RCLK]. 1.544 MHz primary clock.

Used to clock data through the receive side of the

framer.

Receive Channel Clock [RCHCLK]. 192 KHz clock

which pulses high during the LSB of each channel.

Synchronous with RCLK when the receive side elastic

store is disabled. Synchronous with RSYSCLK when

the receive side elastic store is enabled. Useful for par-

allel to serial conversion of channel data, locating

robbed–bit signaling bits, and for blocking clocks in DDS

applications. See Section 12 for timing details.

Receive Channel Block [RCHBLK]. A user program-

mable output that can be forced high or low during any of

the 24 T1 channels. Synchronous with RCLK when the

receive side elastic store is disabled. Synchronous with

RSYSCLK when the receive side elastic store is

enabled. Useful for blocking clocks to a serial UART or

LAPD controller in applications where not all T1 chan-

nels are used such as Fractional T1, 384K bps service,

768K bps, or ISDN–PRI. Also useful for locating individ-

ual channels in drop–and–insert applications and for

per–channel loopback. See Section 12 for timing

details.

021997 8/55

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