PM4314-RI 데이터 시트보기 (PDF) - PMC-Sierra

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PM4314-RI

QUAD T1/E1 LINE INTERFACE DEVICE

PMC-Sierra 

PM4314 QDSX

DATA SHEET

PMC-950857

ISSUE 5

QUAD T1/E1 LINE INTERFACE DEVICE

FIGURE 20- BOUNDARY SCAN ARCHITECTURE........................................ 131

FIGURE 21- TAP CONTROLLER FINITE STATE MACHINE .......................... 133

FIGURE 22- INPUT OBSERVATION CELL (IN_CELL) ................................... 138

FIGURE 23- OUTPUT CELL (OUT_CELL)..................................................... 139

FIGURE 24- BIDIRECTIONAL CELL (IO_CELL)............................................ 140

FIGURE 25- LAYOUT OF OUTPUT ENABLE AND BIDIRECTIONAL CELLS 140

FIGURE 26- B8ZS LINE CODE VIOLATION INSERTION .............................. 141

FIGURE 27- HDB3 LINE CODE VIOLATION INSERTION.............................. 142

FIGURE 28- AMI LINE CODE VIOLATION INSERTION ................................. 143

FIGURE 29- MICROPROCESSOR INTERFACE READ TIMING.................... 150

FIGURE 30- MICROPROCESSOR INTERFACE WRITE TIMING .................. 152

FIGURE 31- XCLK INPUT TIMING FOR JITTER ATTENUATION .................. 153

FIGURE 32- TCLKI INPUT TIMING ................................................................154

FIGURE 33- CLKO8X INPUT TIMING DIAGRAM (FIFO NOT IN TX PATH) ... 156

FIGURE 34- XCLK INPUT TIMING DIAGRAM (FIFO NOT IN TX PATH) ........ 157

FIGURE 35- RCLKO OUTPUT TIMING DIAGRAM......................................... 158

FIGURE 36- JTAG PORT INTERFACE TIMING.............................................. 160

FIGURE 37- ANALOG RECEIVE DATA INPUT TIMING DIAGRAM................ 161

PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE viii

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