UT1750AR(2003) 데이터 시트보기 (PDF) - Aeroflex UTMC
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UT1750AR Datasheet PDF : 55 Pages
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Standard Products
UT1750AR RadHard RISC Microprocessor
Data Sheet
May 2003
FEATURES
q Operates in either RISC (Reduced Instruction Set
Computer) mode or MIL-STD-1750A mode
q Built-in multiprocessor bus arbitration and Direct Memory Access
support (DMA)
q Supports MIL-STD-1750A 32-bit floating-point
operations and 48-bit extended-precision floating-point
operations on chip
q Built-in 9600 baud UART
q Supports defined MIL-STD-1750A Console Mode of Operation
q Full 64K-word address space. Expandable to 1M words with
optional MMU (operand port)
q Register-oriented architecture has 21 user-accessible registers
q Registers may be in 16-bit word or 32-bit double-word
configurations
q TTL-compatible I/O
q Stable 1.5-micron CMOS technology
q Full military operating range, -55°C to +125°C, in accordance
with MIL-PRF-38535 for Class Q and V
q Typical radiation performance
- Total dose: 1.0E6 rads(Si)
- SEL Immune . 100 MeV-cm2/mg
- LETTH(0.25) = 60 MeV-cm2/mg
- Saturated Cross Section (cm2) per bit, 1.2E-7
- 2.3E-11 errors/bit-day, Adams to 90% geosynchronous heavy ion
OE
WE
BRQ
BGNT
BUSY
BGACK
NUI1
NUI2
M1750
STATE1
MME
NUO3
CONSOLE
RISC
MEMORY
CONTROL
OSCOUT
OSCIN SYSCLK
q Standard Military Drawing 5962-01502
16
UART
BUS
ARBITRA-
TION
PROCES-
SOR
STATUS
OSCILLATOR
/CLOCK
GENERAL
PURPOSE
REGISTERS
SHIFT REG 32
32 BIT REG 32
TBR
RBR
T R 16
TB 16
PROCESSOR
CONTROL
LOGIC
TEMP DEST TEMP SRC
IM 16
F R 16
PI 16
I/O
MUX
S T 16
IR
RISC MAP
SW 16
TIMCLK
TEST
UARTOUT
UARTIN
RISC DATA
RISC
ADDRESS 4
or O/P DISC
RISC 16
ADDRESS
SYSFL
BTERR
MPAR
MPROT
PFAIL
IOLINT1
IOLINT0
INT0-5 6
RISC
ADD
MUX
I
N
T
E
R
R
U
P
T
S
16
IC/ICs
32
32
ACC
32
32
32
A MUX
B MUX
32-BIT ALU
8
16
PIPELINE
BUS
PR
CONTROL
1750 SP 16
32
1750 PC 16
16
ADDR
MUX
4 PS0-3
AS0-3
OPERAND
DATA
OP/IN
DTACK
M/IO
R/W R
AS
DS
OPERAND
ADDRESS
MRST
Figure 1. UT1750AR Functional Block Diagram
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