CD40181BMS 데이터 시트보기 (PDF) - Intersil
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CD40181BMS Datasheet PDF : 10 Pages
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CD40181BMS
TABLE A. AC TEST SETUP REFERENCE (ACTIVE LOW DATA)
AC PATHS
DC DATA INPUTS
TEST DELAY TIMES
INPUTS
OUTPUTS
TO VSS
TO VDD
SUMIN to SUMOUT
B0
Any F
B1, B2, B3, M, Cn
All A’s
SUMIN to P
A0
P
A1, A2, A3, M, Cn
All B’s
SUMIN to G
B0
G
All A’s, M, Cn
B1, B2, B3
SUMIN to Cn+4
B0
Cn+4
All A’s, M, Cn
B1, B2, B3
Cn to SUMOUT
Cn
Any F
All A’s, M
All B’s
Cn to Cn+4
Cn
Cn+4
All A’s, M
All B’s
SUMIN to A = B
B0
A=B
All A’s, B1, B2, B3, M Cn
SUMIN to SUMOUT (Logic Mode) All B’s
Any F
All A’s, Cn
M
* Add Mode: S0, S3 = VDD; S1, S2 = VSS.
Subtract Mode: S0, S3 = VSS; S1, S2 = VDD.
MODE*
Add
Add
Add
Add
Add
Add
Subtract
Exclusive OR
TABLE B. MAGNITUDE COMPARISON
ACTIVE HIGH DATA
ACTIVE LOW DATA
INPUT
Cn
OUTPUT
Cn+4
MAGNITUDE
INPUT
Cn
OUTPUT
Cn+4
MAGNITUDE
1
1
0
1
A≤B
A<B
0
0
1
0
A≤B
A<B
1
0
A>B
0
1
A>B
0
0
A≥B
1
1
A≥B
1 = High level 0 = Low level
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are derived from
the basic inch dimensions as indicated. Grid graduations are in mils
(10-3 inch).
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
7-1409
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