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SAA6588

RDS/RBDS pre-processor

Philips Electronics 

Philips Semiconductors

RDS/RBDS pre-processor

Product specification

SAA6588

RDS/RBDS block detection

The RDS/RBDS block detection is always active.

For a received sequence of 26 data bits, a valid block and

its offset are identified via syndrome calculation.

During synchronization search, the syndrome is calculated

with every new received data bit (bit-by-bit) for a received

26-bit sequence. If the decoder is synchronized, syndrome

calculation is activated only after 26 data bits for each new

block received.

Under RBDS reception situation, beside the RDS block

sequences with (A, B, C/C', D) offset also block sequences

of 4 blocks with offset E may be received. If the decoder

detects an E-block, this block is marked in the block

identification number BL and is available via I2C-bus

request. In RBDS processing mode the block is signed as

valid E-block and in RDS processing mode, where only

RDS blocks are expected, signed as invalid E-block

(see Table 13).

This information can be used by the main controller to

detect E-block sequences and identify RDS or RBDS

transmitter stations.

Error detection and correction

The RDS/RBDS error detection and correction recognizes

and corrects potential transmission errors within a

received block via parity-check in consideration of the

offset word of the expected block. Burst errors with a

maximum length of 5 bits are corrected with this method.

After synchronization has been found the error correction

is always active, but cannot be carried out in every

reception situation.

During synchronization search, the error correction is

disabled for detection of the first block and is enabled for

processing of the second block depending on the

pre-selected error correction mode for synchronization

(mode SYNCA to SYNCC, see Table 4).

The processed block data and the status of error

correction are available for data request via I2C-bus for the

last two blocks.

Processed blocks are characterized as uncorrectable

under the following conditions:

• During synchronization search, if the burst error is

higher than allowed by the pre-selected correction

mode.

• After synchronization has been found, if the burst error

is higher than 5 bits or if errors are detected but error

correction is not possible.

Synchronization

The decoder is synchronized if two successive valid blocks

in a valid sequence are detected by the block detection.

For detection of the second block of this sequence, error

correction is also enabled depending on the pre-selected

correction mode (see Table 4). Only valid (correctable)

blocks are accepted for synchronization (see also Section

“Error detection and correction”).

If synchronization is found, the synchronization status flag

(SYNC) is set and available via I2C-bus request.

The synchronization is held until the flywheel

(for synchronization hold) detects a loss of synchronization

(see Section “Flywheel for synchronization hold”) or an

external restart of synchronization is performed (see

Section “Data processing control”).

Flywheel for synchronization hold

For a fast detection of loss of synchronization the internal

flywheel counter checks the number of uncorrectable

blocks (error blocks). Error blocks increment and valid

blocks decrement the block error counter.

The flywheel counter is only active if the decoder is

synchronized. The synchronization is held until the

flywheel counter detects an error block overflow (loss of

synchronization). The maximum value for the error block

counter is adjustable via I2C-bus in a range of 0 to 63

(see Table 6).

The value 32 is set after reset and the values 0 and 63

have a special function.

• If the value 0 is programmed then no flywheel is active

• If the value 63 is programmed then the flywheel is

endless and no new start of synchronization is effected

automatically (synchronization hold).

Bit slip correction

During poor reception situation phase shifts of one bit to

the left or right (±1 bit slip) between the RDS/RBDS clock

and data may occur, depending on the lock conditions of

the demodulators clock regeneration.

If the decoder is synchronized and detects a bit slip, the

synchronization is corrected by +1 or −1 bit via block

detection on the respectively shifted expected new block.

1997 Sep 01

7

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