SY604JC 데이터 시트보기 (PDF) - Micrel
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SY604JC Datasheet PDF : 8 Pages
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Micrel
SY604
PIN DESCRIPTION
D0 – D7
Data input pins (ECL compatible). On the rising edge of TRIG,
a ramp is initiated whereupon D0-D7 are latched into the
device. D0 is the LSB. These inputs specify the amount of
delay from the rising edge of TRIG to the output pulse.
CE
Chip enable input (ECL compatible). CE must be a logical
zero on the rising edge of TRIG to enable the device to
respond to the trigger. If CE is floating, the trigger will always
be enabled.
TRIG, TRIG
Differential trigger inputs (ECL compatible). The rising edge
of TRIG is used to trigger the delay cycle if CE is a logical zero.
If CE is a logical one, no operation occurs. It is recommended
that triggering be performed with differential inputs.
OUT, OUT
Differential outputs (ECL compatible).
IEXT
Current reference pin. The amount of current sourced into this
pin determines the span of output delay. The voltage at IEXT
is typically –1.25V.
COMP1, COMP2
Compensation pins. A 0.1µF ceramic capacitor must be
connected between COMP1 and VEE0, and COMP2 and VEE0
(see Figure 3).
VEE
Device power. All VEE pins must be connected.
VCC
Device ground. All VCC pins must be connected together.
VBB
A –1.36V (typical) output.
FUNCTIONAL DESCRIPTION
The output pulse generation cycle begins with the arrival of
TRIG shown in Figure 1. When TRIG transitions to a high and
CE is low, the values on D0 - D7 are latched, thereby setting
the DAC values. Simultaneously with the latching of D0 - D7,
the linear ramp generator is enabled.
When the ramp level reaches that of the DAC, the
comparator initiates the pulse generator to produce an output
pulse of fixed width. The generation of an output pulse resets
the ramp and the cycle is ready to begin again.
D0 - D7
CE
DATA
TRIG
OUT
Figure 1.
2
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