UT1553 데이터 시트보기 (PDF) - Aeroflex UTMC
부품명
상세내역
제조사
UT1553 Datasheet PDF : 40 Pages
| |||
ADDRESS BUS
NAME
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
PIN NUMBER
LCC
PGA
53
A11
54
B10
55
B9
56
A10
57
A9
58
B8
59
A8
60
C7
61
B7
63
B6
64
C6
65
C5
67
B5
68
A6
69
A4
70
B4
TYPE ACTIVE
DESCRIPTION
TTO
--
Bit 15 (MSB) of the Address bus.
TTO
TTO
--
Bit 14 of the Address bus.
--
Bit 13 of the Address bus.
TTO
--
Bit 12 of the Address bus.
TTO
TTO
--
Bit 11 of the Address bus.
--
Bit 10 of the Address bus.
TTO
TTO
TTO
--
Bit 9 of the Address bus.
--
Bit 8 of the Address bus.
--
Bit 7 of the Address bus.
TTO
TTO
TTO
--
Bit 6 of the Address bus.
--
Bit 5 of the Address bus.
--
Bit 4 of the Address bus.
TTO
--
Bit 3 of the Address bus.
TTB
--
Bit 2 of the Address bus. Address bits A2 - A0 are
bidirectional so the host can select one of the RTMP’s internal
registers during internal I/O operations.
TTB
--
Bit 1 of the Address Bus. (Reference A2)
TTB
--
Bit 0 (LSB) of the Address Bus. (Reference A2)
DMA SIGNALS
NAME
DMAR
DMAG
PIN NUMBER
LCC PGA
47
F11
48
D11
TYPE ACTIVE
DESCRIPTION
TO
AL DMA Request. Indicates the RTMP is requesting
use of the Data bus from the current bus master.
TUI
AL DMA Grant. Gives control of the Data bus to the RTMP.
DMAG is recognized only if DMAEN is high. DMAG must
remain asserted until AV goes high to ensure that the RTMP
completes the current DMA cycle.
DMAEN
49
D10 TUI
AH DMA Enable. When high, this input allows the
RTMP to recognizeDMAG. When low, DMAEN places all
three-state pins in a high-impedance state and disables the
RTMP’s memory access cycle.
RTMP-7
Share Link: 