MC14562B 데이터 시트보기 (PDF) - Motorola => Freescale
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MC14562B Datasheet PDF : 6 Pages
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ÎÎÎÎSÎÎÎÎWIÎÎÎÎTCHÎÎÎÎINGÎÎÎÎCHÎÎÎÎARÎÎÎÎAChCaÎÎÎÎTrEacRtÎÎÎÎeISriTsÎÎÎÎtIiCcSÎÎÎÎ* (CÎÎÎÎL=5ÎÎÎÎ0pFÎÎÎÎ,TAÎÎÎÎ=2ÎÎÎÎ5_CÎÎÎÎ)SymÎÎÎÎbolÎÎÎÎÎÎÎÎVÎÎÎÎDDÎÎÎÎÎÎÎÎÎÎÎÎMinÎÎÎÎÎÎÎÎTÎÎÎÎypÎÎÎÎ# ÎÎÎÎÎÎÎÎMaxÎÎÎÎÎÎÎÎUÎÎÎÎnitÎÎÎÎ
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
Propagation Delay Time
Clock to Q
tPLH, tPHL = (1.7 ns/pF) CL + 515 ns
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 145 ns
tTLH,
ns
tTHL
5.0
—
100
200
10
—
50
100
15
—
40
80
tPLH,
ns
tPHL
5.0
—
600
1200
10
—
250
500
15
—
170
340
Clock Pulse Width
(50% Duty Cycle)
tWH
5.0
600
300
—
ns
10
220
110
—
15
150
75
—
Clock Pulse Frequency
fcl
5.0
—
1.9
1.1
MHz
10
—
5.6
3.0
15
—
8.0
4.0
Data to Clock Setup Time
tsu(1)
5.0
– 20
– 170
—
ns
10
– 10
– 64
—
15
0
– 60
—
tsu(0)
5.0
– 20
– 91
10
– 10
– 58
15
0
– 48
—
ns
—
—
Data to Clock Hold Time
th(1)
5.0
350
263
10
165
109
15
155
100
—
ns
—
—
th(0)
5.0
350
267
10
200
140
15
140
93
—
ns
—
—
Clock Input Rise and Fall Times
tr, tf
5.0
—
—
15
µs
10
—
—
5
15
—
—
4
* The formulas given are for the typical characteristics only at 25_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
DATA
CLOCK
Q16
Q32
Q48
Q64
Q80
Q96
Q112
Q128
7 VSS
CL CL CL CL CL CL CL CL
ID
500 µF
fo
VDD
CLOCK
VSS
DATA
VDD
(f = 1/2 fo)
VSS
Figure 1. Power Dissipation Test Circuit and Waveforms
MOTOROLA CMOS LOGIC DATA
MC14562B
3
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