IS42S16128-10T 데이터 시트보기 (PDF) - Integrated Silicon Solution
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IS42S16128-10T
Integrated Silicon Solution
IS42S16128-10T Datasheet PDF : 75 Pages
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IS42S16128
ISSI ®
AC CHARACTERISTICS(1,2,3)
Symbol
tCK3
tCK2
tAC3
tAC2
tCHI
tCL
tOH3
tOH2
tLZ
tHZ3
tHZ2
tDS
tDH
tAS
tAH
tCKS
tCKH
tCKA
tCS
tCH
tRC
tRAS
tRP
tRCD
tRRD
tDPL3
tDPL2
tDAL3
tDAL2
tT
tREF
Parameter
-8
-10
-12
Min. Max. Min. Max. Min. Max. Units
Clock Cycle Time
Access Time From CLK(4)
CAS Latency = 3 8
—
10
—
12
— ns
CAS Latency = 2 13
—
15
—
17
— ns
CAS Latency = 3 —
6
—
8
—
10 ns
CAS Latency = 2 —
10
—
13
—
15 ns
CLK HIGH Level Width
3
—
4
—
4.5
— ns
CLK LOW Level Width
Output Data Hold Time
3
—
4
—
4.5
— ns
CAS Latency = 3 3
—
4
—
4
— ns
CAS Latency = 2 3
—
4
—
4
— ns
Output LOW Impedance Time
Output HIGH Impedance Time(5)
0
—
0
—
0
— ns
CAS Latency = 3 3
6
4
8
4
10 ns
CAS Latency = 2 3
10
4
12
4
14 ns
Input Data Setup Time
2
—
3
—
3
— ns
Input Data Hold Time
1
—
1.5
—
2
— ns
Address Setup Time
2
—
3
—
3
— ns
Address Hold Time
1
—
1.5
—
2
— ns
CKE Setup Time
2
—
3
—
3
— ns
CKE Hold Time
1
—
1.5
—
2
— ns
CKE to CLK Recovery Delay Time
Command Setup Time (CS, RAS, CAS, WE, DQM)
Command Hold Time (CS, RAS, CAS, WE, DQM)
1CLK+3 — 1CLK+3 — 1CLK+3 — ns
2
—
3
—
3
— ns
1
—
1.5
—
2
— ns
Command Period (REF to REF / ACT to ACT)
80
—
90
—
108
— ns
Command Period (ACT to PRE)
54 12,000 60 12,000 72 12,000 ns
Command Period (PRE to ACT)
24
—
30
—
34
— ns
Active Command To Read / Write Command Delay Time
24
—
30
—
34
— ns
Command Period (ACT [0] to ACT[1])
24
—
30
—
34
— ns
Input Data To Precharge
CAS Latency = 3 1CLK+8 — 1CLK+10 — 1CLK+12 — ns
Command Delay time
CAS Latency = 2 8
—
10
—
12
— ns
Input Data To Active / Refresh
CAS Latency = 3 2CLK+24 — 2CLK+30 — 2CLK+34 — ns
Command Delay time (During Auto-Precharge)
CAS Latency = 2 1CLK+24 — 1CLK+30 — 1CLK+34 — ns
Transition Time
1
30
1
30
1
30 ns
Refresh Cycle Time
—
16
—
16
—
16 ms
Notes:
1. When power is first applied, memory operation should be started 100 µs after Vcc and VccQ reach their stipulated voltages. Also
note that the power-on sequence must be executed before starting memory operation.
2. Measured with tT = 1 ns.
3. The reference level is 1.4 V when measuring input signal timing. Rise and fall times are measured between VIH (min.) and VIL (max.).
4. Access time is measured at 1.4V with the load shown in the figure below.
5. The time tHZ (max.) is defined as the time required for the output voltage to transition by ± 200 mV from VOH (min.) or VOL (max.)
when the output is in the high impedance state.
6
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. A
03/13/00
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